News Column

Researchers Submit Patent Application, "Raid Configuration in a Flash Memory Data Storage Device", for Approval

May 6, 2014



By a News Reporter-Staff News Editor at Information Technology Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Borchers, Albert T. (Aptos, CA); Swing, Andrew T. (Los Gatos, CA); Sprinkle, Robert S. (San Jose, CA), filed on October 18, 2013, was made available online on April 24, 2014.

The patent's assignee is Google Inc.

News editors obtained the following quote from the background information supplied by the inventors: "Data storage devices may be used to store data. A data storage device may be used with a computing device to provide for the data storage needs of the computing device. In certain instances, it may be desirable to store large amounts of data on a data storage device. Also, it may be desirable to execute commands quickly to read data from and to write data to the data storage device."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In a first general aspect, a method of storing data in a flash memory data storage device that includes a plurality of memory chips is disclosed. The method includes determining a number of memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and defining a second partition of the data storage device via a host coupled to the data storage device, where the second partition includes a second subset of the plurality of memory chips. First data is written to the first partition while reading data from the second partition, and first data is written to the second partition while reading data from the first partition.

"Implementations can include one or more of the following features. For example, second data can be written to the first partition, while reading data, and second data can be written to the second partition while reading data from the first partition, and for N=3rd to at least 10th, or at least 100th, or at least 1000th: N data can be written to the first partition, while reading data from the second partition, and N data can be written to the second partition while reading data from the first partition.

"Determining a number memory chips in the data storage device can include transmitting information from the data storage device to the host indicating the number of memory chips in the data storage device, and the transmitted information can include information about the physical architecture of the data storage device, including information about connections between particular memory chips and particular channels of the data storage device. An address location in the data storage device to which to write data from the host, can be defined in the host, where the address location specifies that the data be written to a specific one of the plurality of memory chips.

"The data storage device can include a plurality of physical channels for communication of data between the host and the plurality of memory chips, with each channel being operably connected to a different plurality of the memory chips, and the method further include determining a number of the physical channels, determining a first subset of the number channels, where channels of the first subset of channels are operably connected only to memory chips of the first subset of memory chips, and determining a second subset of the number of channels, where channels of the second subset of channels are operably connected only to memory chips of the second subset of memory chips. An address location in the data storage device to which to write data from the host can be defined in the host, where the address location specifies that the data be written to a specific one of the plurality of memory chips through a specific channel. In addition, the data storage device can include a plurality of physical channels for communication of data between the host and the plurality of memory chips, and the method can further include determining a number of the physical channels, where the determined channels are operably connected to memory chips of the first subset of memory chips and are operably connected to memory chips of the second subset of memory chips.

"The first subset may not include any memory chips of the second subset, and the second subset may not include any memory chips of the first subset. The method may further include receiving an indication that a memory chip of the first partition has failed or is likely to fail, re-defining, via the host coupled to the data storage device, the first partition of the data storage device to include a third subset of the plurality of memory chips, where the third subset is different from the first subset, and where the third subset does not include any memory chips of the second subset and where the second subset does not include any memory chips of the third subset. Re-defining the first partition can include defining the third subset as the first subset of memory chips but for the memory chip that has failed or that is approaching failure.

"In another general aspect, an apparatus includes a flash memory data storage device including a plurality of memory chips, and a host operably coupled to the data storage device via an interface. The host includes a configuration detection engine configured to detect a number of memory chips in the data storage device, a partition engine, and a driver. The partition engine configured to define a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and a second partition of the data storage device, where the second partition includes a second subset of the plurality of memory chips. The driver is configured to write first data to the first partition, read data from the second partition while the first data is being written to the first partition, and write the first data to the second partition while reading data from the first partition.

"Implementations can include one or more of the following features. For example, the driver can be further configured to write second data to the first partition while reading data from the second partition and to write the second data to the second partition while reading data from the first partition; and for N=3rd to at least 10th the driver can be further configured to write N data to the first partition, while reading data from the second partition to write the N data to the second partition while reading data from the first partition.

"The data storage device can be configured to transmit, upon receiving a command from the host, information from the data storage device to the host indicating the number of memory chips in the data storage device, and the transmitted information can include information about the physical architecture of the data storage device, including information about connections between particular memory chips and particular channels of the data storage device. The host can further include an address assignment engine configured to assign a memory address to data to be written to the data storage device, where the assigned memory address specifies that the data be written to a specific one of the plurality of memory chips.

"When the data storage device includes a plurality of physical channels for communication of data between the host and the plurality of memory chips, with each channel being operably connected to a different plurality of the memory chips, the configuration detection engine can be further configured to detect a number of the physical channels, and the partition engine can be further configured to determine a first subset of the number channels, where channels of the first subset of channels are operably connected only to memory chips of the first subset of memory chips and to determine a second subset of the number of channels, where channels of the second subset of channels are operably connected only to memory chips of the second subset of memory chips. The address assignment engine can be configured to assign a memory address to data to be written to the data storage device, where the assigned memory address specifies that the data be written to a specific one of the plurality of memory chips through a specific channel. In another implementation, when the data storage device includes a plurality of physical channels for communication of data between the host and the plurality of memory chips, the plurality of physical channels can be operably connected to memory chips of the first subset of memory chips and operably connected to memory chips of the second subset of memory chips.

"The partition engine is further configured to receive an indication that a memory chip of the first partition has failed o is likely to fail, to re-define the first partition of the data storage device to include a third subset of the plurality of memory chips, where the third subset is different from the first subset, and where the third subset does not include any memory chips of the second subset and where the second subset does not include any memory chips of the third subset.

"The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is an exemplary block diagram of a data storage device.

"FIG. 2 is an exemplary perspective block diagram of the printed circuit boards of the data storage device.

"FIG. 3A is an exemplary block diagram of exemplary computing devices for use with the data storage device of FIG. 1.

"FIG. 3B is an exemplary block diagram of exemplary computing devices for use with the data storage device of FIG. 1.

"FIG. 4 is an exemplary flowchart illustrating an example process of storing data on the data storage device of FIG. 1.

"FIG. 5 is an exemplary block diagram of an example implementation of the data storage device of FIG. 1.

"FIG. 6 is an exemplary flowchart illustrating example operations of the data storage device of FIG. 1."

For additional information on this patent application, see: Borchers, Albert T.; Swing, Andrew T.; Sprinkle, Robert S. Raid Configuration in a Flash Memory Data Storage Device. Filed October 18, 2013 and posted April 24, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=572&p=12&f=G&l=50&d=PG01&S1=20140417.PD.&OS=PD/20140417&RS=PD/20140417

Keywords for this news article include: Google Inc., Information Technology, Information and Data Storage.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Information Technology Newsweekly


Story Tools






HispanicBusiness.com Facebook Linkedin Twitter RSS Feed Email Alerts & Newsletters