News Column

Researchers Submit Patent Application, "Gang Programming of Devices", for Approval

May 8, 2014



By a News Reporter-Staff News Editor at Politics & Government Week -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Sleator, Michael (Woodside, CA); Stubbs, Mark Adrian (Felton, CA), filed on July 11, 2013, was made available online on April 24, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "The Joint Test Action Group ('JTAG') standard is codified in the IEEE 1149.1-1993 Standard Test Access Port and Boundary-Scan Architecture. Presently, there are multiple IEEE 1149 versions, including 1149.1, 1149.6, and 1149.7 (hereinafter 1149.X refers to any version of the IEEE 1149.1-1993 protocols, including 1149.1). JTAG is primarily used to test printed circuit boards and debug integrated circuits. It is incorporated into many electronic devices such as cell phones or wireless access points. In addition, JTAG may be used to program data into non-volatile memory devices such as a complex programmable logic device ('CPLD') or flash memory.

"Typically, a JTAG interface has at least four or five pins, corresponding to Test Data In ('TDI'), Test Data Out ('TDO'), Test Clock ('TCK'), Test Mode Select ('TMS'), and, optionally, a Test Reset (TRST). A series of JTAG compliant devices may be 'daisy-chained' or connected serially to one another in accordance with IEEE 1149.X. For example, the TDO output of a JTAG controller (host device) is received at the TDI input of a test access port ('TAP') controller of the first device. The first device then outputs the data (as TDO) to a second device, where it is received as TDI (e.g., at a TAP controller of the second device). That is, the TDI pin of the first device is driven by the JTAG controller (input device) and TDO of the first device drives the TDI pin of the next device in the chain. If the second device is the last device in the chain, then it sends the data as TDO to the JTAG controller (input or host device). The JTAG controller also transmits TMS and TCK to each device in the chain. Thus, the JTAG controller transmits data to the first device in the chain. Upon receiving the TDO from the last device in the chain, the JTAG controller of the host device (e.g., input device) may then compare TDI to TDO to determine whether they are the same. TDO should equal TDI when there have been no errors in transmitting the data to the devices in the chain. Thus, JTAG implements a system that can program devices arranged in a series. The inability to program multiple devices simultaneously, however, may impede a production process flow."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "In an implementation, a first TAP controller of an IEEE 1149.X compliant master device may receive a first data. The master device may be programmed with the first data. For example, the first data may be stored in a programmable module of the master device such as an instruction register or computer readable storage. A second data may be generated subsequent to the programming of the master device with the first data. The second data may be transmitted to a first logic circuit and a second logic circuit. A second TAP controller of an IEEE 1149.X compliant first slave device may receive the first data. The receipt of the data by the first slave device may be concurrent with the receipt of the first data by the master device. The first slave device may be programmed with the first data. A third data may be generated subsequent to the programming of the first slave device with the first data. The third data may be transmitted to the first logic circuit. A third TAP controller of an IEEE 1149.X compliant second slave device may receive the first data. As above, it may receive the first data concurrently with the master device and the first slave device. The second slave device may be programmed with the first data. A fourth data may be generated subsequent to the programming of the second slave device with the first data. The fourth data may be transmitted to the second logic circuit. The first logic circuit may compare the second data to the third data. The result of the comparison may be signaled, for example, by a LED. The second logic circuit may compare the second data to the fourth data and signal the result of the comparison.

"In an implementation, a first master device and a first slave device may receive a first data. At least one of the first master device or the first slave device may be substantially JTAG or IEEE 1149.X compliant. The first data may be, for example, an instruction. The first data may be stored to a first programming module belonging to the first master device and a second programming module belonging to the first slave device. Storage of the first data to the first slave device may cause it to be programmed. A second data may be generated subsequent to programming the first master device with the first data. The first data may be identical to the second data. A third data may be generated subsequent to programming the first slave device. The second data and the third data may be sent to a first logic circuit. The first logic circuit may compare the second data to the third data and signal the result of the comparison.

"In some configurations, multiple slave devices may be present. A second slave device may receive the first data and store the first data to a programming module. As above, storage of the first data to the slave device may cause the device to be programmed. A fourth data may be generated upon storage of the first data to the third programming module. The second data and the fourth data may be sent to a second logic circuit and the second data may also be sent to the second. The second logic circuit may compare the second data to the fourth data and signal the result of the comparison.

"Typically, a single logic circuit may be associated with each slave device and be physically independent from each slave device and master device (notwithstanding connections to the master and slave device). In some configurations a single logic circuit may be utilized to perform multiple pairwise comparisons of data between one or more master devices and one or more slave devices. In some configurations, it may be desirable to have logic circuits on board a slave device. Depending on the outcome of a comparison, a logic circuit may be latched. In some configurations, depending on the number of devices involved in the system, it may be necessary to provide one or more buffer amplifiers. For example, a buffer amplifier may be disposed between the host device and master device and one or more slave device. It may facilitate providing the first data to the master device and the one or more slave devices. Similarly, a buffer amplifier may be disposed between the master device and a second master device or between a master device and one or more logic circuits.

"According to an implementation, a second master device my receive the second data and store it to a fourth programmable module. A fifth data may be generated upon storage of the second data by the second master device. The fifth data may be sent to a third logic circuit. A third slave device may receive the second data and store it to a fifth programming module, thereby programming the third slave device. A sixth data may be generated subsequent to programming the third slave device. The sixth data may be sent to the third logic circuit. The third logic circuit may compare the fifth data to the sixth data and signal the result of the comparison.

"Also disclosed is a system that contains a master device, a first slave device, and a first logic circuit. The master device may have a first controller (e.g., a TAP controller) and a first programmable module. The first slave device may include a second controller and a second programmable module. The master device may be configured to receive a first data by the first controller and program the first programmable module with the first data. The master device may generate a second data subsequent to storing the first data in the first programmable module and send the second data to the first logic circuit. The first slave device may be configured to receive the first data by the second controller. It may store the first data in the second programmable module, thereby programming the first slave device. The first slave device may generate a third data based upon the result of the step of programming the second programmable module. It may send the third data to the first logic circuit. The first logic circuit may be configured to compare the second data to the third data to determine whether the second data matches the third data; and signal the result of the step of comparing the second data to the third data.

"The system may also include a second logic circuit and a second slave device that has a third controller and a third programmable module. The second slave device may be configured to receive the first data by the third controller and program the third programmable module utilizing the first data. The second slave device may generate a fourth data subsequent to storing the first data to the third programmable module and it may send the fourth data to the second logic circuit. The second logic circuit may compare the second data to the fourth data to determine whether the second data matches the fourth data and signal the result of the comparison.

"Additional features, advantages, and implementations of the disclosed subject matter may be set forth or apparent from consideration of the following detailed description, drawings, and claims. Moreover, it is to be understood that both the foregoing summary and the following detailed description are examples and are intended to provide further explanation without limiting the scope of the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

"The accompanying drawings, which are included to provide a further understanding of the disclosed subject matter, are incorporated in and constitute a part of this specification. The drawings also illustrate implementations of the disclosed subject matter and together with the detailed description serve to explain the principles of implementations of the disclosed subject matter. No attempt is made to show structural details in more detail than may be necessary for a fundamental understanding of the disclosed subject matter and various ways in which it may be practiced.

"FIG. 1 shows a computer according to an implementation of the disclosed subject matter.

"FIG. 2 shows a network configuration according to an implementation of the disclosed subject matter.

"FIG. 3 shows an example process flow of programming master and slave devices simultaneously according to an implementation disclosed herein.

"FIG. 4 shows an example of information flow according to an implementation of the disclosed subject matter.

"FIG. 5 shows an example arrangement of master and slave devices and data flow according to an implementation of the disclosed subject matter.

"FIG. 6 shows an example logic circuit arrangement for a device configuration as shown in FIG. 5."

For additional information on this patent application, see: Sleator, Michael; Stubbs, Mark Adrian. Gang Programming of Devices. Filed July 11, 2013 and posted April 24, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=593&p=12&f=G&l=50&d=PG01&S1=20140417.PD.&OS=PD/20140417&RS=PD/20140417

Keywords for this news article include: Patents.

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Source: Politics & Government Week


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