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Researchers Submit Patent Application, "Multi-Layer Type Coreless Substrate and Method of Manufacturing the Same", for Approval

May 7, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Kim, Da Hee (Suwon, KR); Oh, Yoong (Suwon, KR); Yoo, Ki Young (Suwon, KR); Lee, Han Ul (Suwon, KR); Kang, Myung Sam (Suwon, KR); Kim, Ki Hwan (Suwon, KR), filed on March 14, 2013, was made available online on April 24, 2014.

The patent's assignee is Samsung Electro-mechanics Co., Ltd.

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to a multi-layer type coreless substrate and a method of manufacturing the same.

"Generally, a printed circuit board is implemented by wiring a copper foil on one surface or both surfaces of a board made of various kinds of thermosetting synthetic resins, fixing IC or electronic components on the board, and implementing electrical wirings therebetween and then, coating the electrical wirings with an insulator.

"Recently, with the development of electronic industries, a demand for multi-functional and light and small electronic components has been rapidly increased. Accordingly, there is a need to increase a wiring density of a printed circuit board on which the electronic components are mounted and reduce a thickness thereof.

"In particular, in order to cope with the thinness of the printed circuit board, a coreless substrate with the reduced thickness and signal processing time by removing a core substrate has been spotlighted. In case of the coreless substrate, since the core substrate is removed, a carrier member serving as a support during a manufacturing process is required.

"An upper substrate and a lower substrate are separated from each other by forming a buildup layer including circuit layers and insulating layers on both surfaces of the carrier member according to a method of manufacturing a substrate of the prior art and removing the carrier member, such that the coreless substrate is completed.

"As described in Patent Document 1, the method of manufacturing a coreless substrate of the prior art performs a laser direct ablation (LDA) method of forming opening parts on an insulating layer as a previous stage for forming vias for electrical connection of each buildup layer.

"However, the LDA method may cause an increase in machining time due to a limitation of a laser spot size when a size of the opening part is large.

"Further, the method of manufacturing a coreless substrate according to the prior art need to perform laser machining several times, thereby increasing complexity and costs of process."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "The present invention has been made in an effort to provide a multi-layer type coreless substrate on which a plurality of pillars for electrically connecting buildup layers using a dry film are formed.

"Further, the present invention has been made in an effort to provide a method of manufacturing a multi-layer type coreless substrate on which a plurality of pillars for electrically connecting buildup layers using a dry film are formed.

"According to a preferred embodiment of the present invention, there is provided a multi-layer type coreless substrate, including: a first insulating layer including at least one first pillar; a plurality of insulating layers laminated on one surface or both surfaces of the first insulating layer, each including at least one circuit layer and at least another pillar connected to the circuit layer; and a plurality of outermost circuit layers contacting a pillar disposed on an outermost insulating layer of the plurality of insulating layers.

"The circuit layers may symmetrically contact each other on both surfaces thereof, based on the first pillar and the pillars each connected with the circuit layers symmetrically contacting each other may be symmetrically provided based on the first pillar.

"The outermost circuit layer may be provided with a first surface treating film or a second surface treating layer.

"The circuit layers and other pillars may be sequentially disposed repeatedly, by including the circuit layer contacting the first pillar and the pillar connected to the circuit layer.

"The first surface treating film may be formed of any one of an organic solderability preservative (OSP) treating film, a black oxide film, and a brown oxide film, instead of a solder resist (SR).

"The second surface treating film may be formed of any one of a gold plating film, an electrolytic gold plating film, an electroless gold plating film, and an electroless nickel immersion gold (ENIG) film.

"According to an another preferred embodiment of the present invention, there is provided a method of manufacturing a multi-layer type coreless substrate, including: (A) preparing a carrier substrate including an insulating plate having at least one copper foil disposed on one surface or both surfaces thereof; (B) forming a plurality of first pillars on one surface or both surfaces of the carrier substrate using a first dry film pattern; (C) thermo-compressing a first compression layer sequentially including a first insulating layer and a first metal foil to one surface or both surfaces of the carrier substrate; (D) removing a protruded portion of the first metal foil and forming a circuit layer on an outer surface of a first insulating layer on which the first pillar is exposed; (E) forming a plurality of second pillars connected with the circuit layer using a second dry film pattern disposed on the outer surface of the first insulating layer; (F) thermo-compressing a second compression layer sequentially including a second insulating layer and a second metal foil to the outer surface of the first insulating layer on which the second pillar is disposed; (E) separating the carrier substrate; and (H) removing a protruded portion of the second metal foil and laminating a plurality of other insulating layers on which other circuit layers and other pillars are sequentially disposed on an outer surface of the second insulating layer on which the second pillar is exposed or the outer surface of the first insulating layer on which the first pillar is exposed.

"The method of manufacturing a multi-layer type coreless substrate may further include: (I) forming an outermost circuit layer on an outermost insulating layer of the other insulating layers; and (J) forming a first surface treating film or a second surface treating film on the outermost circuit layer.

"The step (B) may include: (B-1) forming a seed layer on one surface or both surfaces of the carrier substrate; (B-2) forming the first dry film pattern on the seed layer; (B-3) plating copper on the first dry film pattern by a chemical copper plating method; and (B-4) peeling off the first dry film pattern.

"In the step (C), the first insulating layer in a non-cured state may be thermo-compressed to the first pillar using a thermo-compression jig.

"In the step (C), a height t of the first pillar may be formed in a range of 1.1 to 2.0 times as much as a thickness T of the first insulating layer.

"The step (D) may include: (D-1) performing a partial polishing process for removing a protruded portion of the first metal foil; (D-2) forming a seed layer on the outer surface of the first insulating layer on which the first pillar is exposed; and (D-3) forming the circuit layer by performing any one of an additive method using chemical copper plating, a semi-additive process (SAP) and a modified semi-additive process (MSAP) on the seed layer.

"In the step (D-1), the partial polishing process may use an end-mill.

"The step (E) may include: (E-1) forming a seed layer on the outer surface of the first insulating layer; (E-2) forming a second dry film pattern on the seed layer; (E-3) plating copper on the second dry film pattern by a chemical copper plating method to form the second pillar; and (E-4) peeling off the second dry film pattern.

"In the step (F), the second insulating layer in a non-cured state may be thermo-compressed to the second pillar using a thermo-compression jig.

"The step (H) may include: (H-1) performing a partial polishing process for removing a protruded portion of the second metal foil; (H-2) forming another seed layer on the outer surface of the second insulating layer on which the second pillar is exposed or the outer surface of the first insulating layer on which the first pillar is exposed; (H-3) forming the other circuit layers by performing any one of an additive method using chemical copper plating, a semi-additive process (SAP) and a modified semi-additive process (MSAP) on another seed layer; (H-4) forming other dry film patterns on the other circuit layers; (H-5) plating copper on the other dry film patterns by a chemical copper plating method to form the plurality of other pillars connected with the other circuit layers; (H-6) peeling off the other dry film patterns; and (H-7) thermo-compressing other compression layers on which the other insulating layers and the other metal foils are sequentially disposed to other seed layers including the other pillars, wherein the steps (H-1) to (H-7) are repeatedly performed.

"According to still preferred embodiment of the present invention, there is provided a method of manufacturing a multi-layer type coreless substrate, including: (I) preparing a carrier substrate including an insulating plate having at least one copper foil disposed on one surface or both surfaces thereof; (II) forming a plurality of first pillars on one surface or both surfaces of the carrier substrate using a first dry film pattern; (III) thermo-compressing a first compression layer sequentially including a first insulating layer and a first metal foil to one surface or both surfaces of the carrier substrate; (IV) separating the carrier substrate; (V) removing a protruded portion of the first metal foil and laminating a plurality of other insulating layers in which other circuit layers and other pillars are sequentially disposed on one surface or both surface outside the first insulating layer on which the first pillar is exposed using the first metal foil as a seed layer; (VI) forming an outermost circuit layer on an outermost insulating layer of the other insulating layers; and (VII) forming a first surface treating film or a second surface treating film on the outermost circuit layer.

"The step (II) may include: (II-1) forming the first dry film pattern on a copper foil using the copper foil of the carrier substrate as the seed layer; (II-2) plating copper on the first dry film pattern by a chemical copper plating method to form the plurality of first pillars; and (II-3) peeling off the first dry film pattern.

"The step (V) may include: (V-1) performing a partial polishing process for removing a protruded portion of the first metal foil; (V-2) forming the other circuit layers by any one of an additive method using chemical copper plating, a semi-additive process (SAP) and a modified semi-additive process (MSAP) using the first metal foil as the seed layer; (V-3) forming other dry film patterns on the other circuit layers; (V-4) plating copper on the other dry film patterns by a chemical copper plating method to form the plurality of other pillars connected with the other circuit layers; (V-5) peeling off the other dry film patterns; and (V-6) thermo-compressing other compression layers on which other insulating layers and other metal foils are sequentially disposed to other circuit layers including the other pillars, wherein the steps (V-1) to (V-6) may be repeatedly performed.

"In the step (V-1), an end-mill may be used.

BRIEF DESCRIPTION OF THE DRAWINGS

"The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

"FIG. 1 is a cross-sectional view of a multi-layer type coreless substrate according to a first preferred embodiment of the present invention;

"FIGS. 2A to 2O are cross-sectional views sequentially showing the processes of a method of manufacturing a multi-layer type coreless substrate according to the first preferred embodiment of the present invention;

"FIGS. 3A to 3O are cross-sectional views sequentially showing the processes of a method of manufacturing a multi-layer type coreless substrate according to a second preferred embodiment of the present invention;

"FIGS. 4A to 4D are cross-sectional views sequentially showing the processes of a method of manufacturing a multi-layer type coreless substrate according to a third preferred embodiment of the present invention; and

"FIG. 5 is a cross-sectional view of a multi-layer type coreless substrate according to a fourth preferred embodiment of the present invention."

For additional information on this patent application, see: Kim, Da Hee; Oh, Yoong; Yoo, Ki Young; Lee, Han Ul; Kang, Myung Sam; Kim, Ki Hwan. Multi-Layer Type Coreless Substrate and Method of Manufacturing the Same. Filed March 14, 2013 and posted April 24, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=6513&p=131&f=G&l=50&d=PG01&S1=20140417.PD.&OS=PD/20140417&RS=PD/20140417

Keywords for this news article include: Circuit Board, Electronic Components, Samsung Electro-mechanics Co. Ltd.

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Source: Electronics Newsweekly


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