News Column

Patent Issued for Trench Junction Field-Effect Transistor

May 7, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Alexandria, Virginia, by VerticalNews journalists, a patent by the inventor Yang, Robert Kuo-Chang (Campbell, CA), filed on February 29, 2012, was published online on April 22, 2014.

The assignee for this patent, patent number 8704296, is Fairchild Semiconductor Corporation (San Jose, CA).

Reporters obtained the following quote from the background information supplied by the inventors: "Known junction field-effect transistor (JFET) devices manufactured using known semiconductor processing techniques can have a relatively large circular footprint within a semiconductor die. Often these known JFET devices are separately manufactured in different areas of a layout from other semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs). Because the JFET devices can be in completely separate areas of the die from MOSFET devices, the overall layout of the die can have undesirable inefficiencies. Thus, a need exists for systems, methods, and apparatus to address the shortfalls of present technology and to provide other new and innovative features."

In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "In a general aspect, a semiconductor device can include a gate having a first trench portion disposed within a first trench of a junction field-effect transistor device, a second trench portion disposed within a second trench of the junction field-effect transistor device, and a top portion coupled to both the first trench portion and to the second trench portion. The semiconductor device can include a mesa region disposed between the first trench and the second trench, and including a single PN junction defined by an interface between a substrate dopant region having a first dopant type and a channel dopant region having a second dopant type.

"In another general aspect, an apparatus can include a source, and a gate electrically isolated from the source where the gate has a trench portion disposed within a first trench of a junction field-effect transistor device and has a trench portion disposed within a second trench of the junction field-effect transistor device. The apparatus can include a member disposed within the first trench and capacitively coupled to the trench portion of the gate disposed within the first trench. The member can have a trench width less than a trench width of the trench portion of the gate disposed within the first trench, and a channel dopant region in contact with the source and continuously extending into a mesa region disposed between the first trench and the second trench.

"In yet another general aspect, an apparatus can include a gate of a junction field-effect transistor coupled to a gate oxide, and a P-type substrate of the junction field-effect transistor. The apparatus can also include an N-type dopant region disposed between the gate oxide and the P-type substrate, the N-type dopant region being in contact with the gate oxide.

"The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims."

For more information, see this patent: Yang, Robert Kuo-Chang. Trench Junction Field-Effect Transistor. U.S. Patent Number 8704296, filed February 29, 2012, and published online on April 22, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=74&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3681&f=G&l=50&co1=AND&d=PTXT&s1=20140422.PD.&OS=ISD/20140422&RS=ISD/20140422

Keywords for this news article include: Electronics, Fairchild Semiconductor Corporation.

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Source: Electronics Newsweekly


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