News Column

Patent Issued for Method for Manufacturing Semiconductor Device Having a Wiring Structure

May 7, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- Fujitsu Semiconductor Limited (Yokohama, JP) has been issued patent number 8703606, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventor is Kirimura, Tomoyuki (Yokohama, JP).

This patent was filed on February 1, 2012 and was published online on April 22, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "According to a large scale and highly integrated semiconductor device in recent years, a design rule of wirings is also miniaturized in accordance with generation. Conventionally, the wirings are formed by performing a patterning of a conductive material by using lithography and dry etching after the conductive material is deposited on an insulating film. However, a technical limit begins to occur as the generation proceeds. Accordingly, a method so-called a damascene wiring in which wiring trenches and connection holes are formed at the insulating film, and thereafter, a wiring material is embedded in the wiring trenches and the connection holes to form the wiring structure is used as a new formation process of wiring taking over the conventional formation process. It is easy for the damascene process to form a wiring layer by using a low-resistance conductive material such as copper which is difficult to perform the dry etching, and it is extremely effective to form a fine and low-resistance wiring structure.

"There are a single damascene method in which the wiring trenches and the connection holes are embedded separately with the conductive material, and a dual damascene method in which the wiring trenches and the connection holes (via holes) are simultaneously embedded with the conductive material in the damascene wiring. Between them, the embedding of the conductive material to the wiring trenches and the via holes is performed by one time process in the dual damascene method, and therefore, there is an advantage in which a manufacturing method is simplified compared to the single damascene method.

"In the dual damascene method, there are a via-first method (refer to Patent Document 1) forming the via holes first and a trench-first method (refer to Patent Document 2) forming the wiring trenches first.

"In the dual damascene method, problems such that a diameter of the via hole becomes small, and a leakage current occurs between adjacent wirings occur if a positional displacement between the via holes and the wiring trenches occurs when the via holes and the wiring trenches are formed. Patent Document 1: Japanese Laid-open Patent Publication No. 11-274299 Patent Document 2: Japanese Laid-open Patent Publication No. 11-186274"

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "An aspect of a manufacturing method of a semiconductor device, includes: forming a first interlayer insulating film above a semiconductor substrate; forming a wiring layer in the first interlayer insulating film; forming a second interlayer insulating film above the first interlayer insulating film and the wiring layer; forming a first mask layer above the second interlayer insulating film and forming a second mask layer above the first mask layer; forming a first opening portion in the second mask layer; forming a resist layer including a second opening portion above the second mask layer at a position at least partially overlapping with the first opening portion; performing a first etching in which the first mask layer is etched while using the resist layer as a mask or the resist layer and the second mask layer as masks; performing a second etching in which the first mask layer is etched in a direction parallel to a surface of the semiconductor substrate after the performing the first etching; forming connection holes in the second interlayer insulating film by etching the second interlayer insulating film while using the first mask layer and the second mask layer as masks after the performing the second etching; forming wiring trenches in the second interlayer insulating film by etching the first mask layer and the second interlayer insulating film while using the second mask layer as a mask after the forming the connection holes; and forming a conductive film in the connection holes and the wiring trenches.

"Another aspect of a manufacturing method of a semiconductor device includes: forming a first interlayer insulating film above a semiconductor substrate; forming a wiring layer in the first interlayer insulating film; forming a second interlayer insulating film above the first interlayer insulating film and the wiring layer; forming a first mask layer above the second interlayer insulating film, forming a second mask layer above the first mask layer, and forming a third mask layer above the second mask layer; forming a first opening portion in the third mask layer; forming a resist layer including a second opening portion above the third mask layer at a position at least partially overlapping with the first opening portion; performing a first etching in which the second mask layer is etched while using the resist layer and the third mask layer as masks; performing a second etching in which the second mask layer is etched in a direction parallel to a surface of the semiconductor substrate after the performing the first etching; forming connection holes in the second interlayer insulating film by etching the first mask layer and the second interlayer insulating film while using the third mask layer and the second mask layer as masks after the performing the second etching; forming wiring trenches in the second interlayer insulating film by etching the second mask layer, the first mask layer and the second interlayer insulating film while using the third mask layer as a mask after the forming the connection holes; forming a conductive film in the connection holes and the wiring trenches; and removing the first mask layer, the second mask layer, and the conductive film above the second interlayer insulating film by polishing after the depositing the conductive film.

"The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

"It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed."

For the URL and additional information on this patent, see: Kirimura, Tomoyuki. Method for Manufacturing Semiconductor Device Having a Wiring Structure. U.S. Patent Number 8703606, filed February 1, 2012, and published online on April 22, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=88&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=4365&f=G&l=50&co1=AND&d=PTXT&s1=20140422.PD.&OS=ISD/20140422&RS=ISD/20140422

Keywords for this news article include: Electronics, Fujitsu Semiconductor Limited.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


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Source: Electronics Newsweekly


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