News Column

Patent Application Titled "Three Dimensional Stacked Semiconductor Structure and Method for Manufacturing the Same" Published Online

May 7, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors Lai, Erh-Kun (Taichung City, TW); Shih, Yen-Hao (New Taipei City, TW), filed on October 16, 2012, was made available online on April 24, 2014.

The assignee for this patent application is Macronix International Co., Ltd.

Reporters obtained the following quote from the background information supplied by the inventors: "The disclosure relates in general to a three-dimensional (3D) stacked semiconductor structure and method of manufacturing the same, and more particularly to the 3D stacked semiconductor structure in a fan-out region of a 3D flash memory and method of manufacturing the same.

"A nonvolatile semiconductor memory device is typically designed to securely hold data even when power is lost or removed from the memory device. Various types of nonvolatile memory devices have been proposed in the related art. Also, manufactures have been looking for new developments or techniques combination for stacking multiple planes of memory cells, so as to achieve greater storage capacity. For example, several types of multi-layer stackable thin-film transistor (TFT) NAND-type flash memory structures have been proposed.

"With the development of size reduction of device, the distance between gates in the array region of the three-dimensional (3D) stacked flash memory structure is reduced consequently. Take a 3D NAND-type flash memory structure as an example. Without ion implant, the junctions between the gates still occur after voltage applies to the structure (so called as a 3D stacked junction-free NAND structure). FIG. 1 is a perspective view of part of a 3D stacked NAND flash memory. The 3D stacked NAND flash memory includes an array region 11 and a fan-out region 13. The 3D stacked semiconductor structure in the fan-out region 13 comprises a stack of several oxide layers 131 and polysilicon layers 133 (as gate material) arranged alternately. The contact holes 135 is formed vertically to the stack and filled with conductors for connecting each of the conductive layers to outer circuits. However, the resistances of the polysilicon layers 133 in the fan-out region 13 have to be decreased by ion implanting. High resistances of the polysilicon layers 133 would have considerable effect on the programming speed (e.g. read latency) of the 3D stacked flash memory, such as causing response delay or even out of operation. Currently, the polysilicon layers 133 in the fan-out region 13 are ion implanted layer by layer, which is time-consuming and expansive."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "The disclosure relates to a three-dimensional (3D) stacked semiconductor structure and method of manufacturing the same. The resistance of the 3D stacked semiconductor structure could be effectively reduced by simple manufacturing procedures provided in the embodiments, and the operation speed of the structure is consequently increased. Accordingly, the 3D stacked semiconductor structure provided in the embodiments have low production cost due to simple and quick manufacturing steps, and the applied memory possesses improved speed, and high and stable performance.

"According to one embodiment of the present disclosure, a 3D stacked semiconductor structure is provided, comprising a stack including plural oxide layers and conductive layers arranged alternately, at least a contact hole formed vertically to the oxide layers and the conductive layers, and the contact hole extending to one of the conductive layers, an insulator formed at the sidewall of the contact hole, a conductor formed in the contact hole and connecting the corresponding conductive layer, and the corresponding conductive layer comprises a silicide. The silicide could be formed at edges or an entire body of the corresponding conductive layer. Besides the silicide, the corresponding conductive layer of the embodiments could further, partially or completely, comprise a conductive material (as a conducting substance) connected to the conductor. The corresponding conductive layer which the contact hole extends to has higher conductivity than other conductive layers.

"According to one embodiment of the present disclosure, a method of forming 3D stacked semiconductor structure is provided, comprising steps of forming a plurality of oxide layers and a plurality of conductive layers arranged alternately; forming at least a contact hole vertically to the oxide layers and the conductive layers, and the contact hole extending to one of the conductive layers; forming an insulator at sidewall of the contact hole; forming a conductor in the contact hole, and the conductor connecting the corresponding conductive layer which the contact hole extends to; and at least forming a silicide at one portion of corresponding conductive layer which the contact hole extends to. The corresponding conductive layer which the contact hole extends to has higher conductivity than other conductive layers. In the embodiments, the silicide could be formed before or after forming the contact hole and the insulator.

"The disclosure will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 (prior art) is a perspective view of part of a 3D stacked NAND flash memory.

"FIG. 2 is a cross-sectional view of a 3D stacked semiconductor structure according to the embodiment of the present disclosure.

"FIG. 3A-FIG. 3G illustrates a method for manufacturing a 3D stacked semiconductor structure of FIG. 2.

"FIG. 4 is a cross-sectional view of another 3D stacked semiconductor structure according to the embodiment of the present disclosure.

"FIG. 5 is a cross-sectional view of a yet another 3D stacked semiconductor structure according to the embodiment of the present disclosure.

"FIG. 6 is a cross-sectional view of a further 3D stacked semiconductor structure according to the embodiment of the present disclosure."

For more information, see this patent application: Lai, Erh-Kun; Shih, Yen-Hao. Three Dimensional Stacked Semiconductor Structure and Method for Manufacturing the Same. Filed October 16, 2012 and posted April 24, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5749&p=115&f=G&l=50&d=PG01&S1=20140417.PD.&OS=PD/20140417&RS=PD/20140417

Keywords for this news article include: Electronics, Semiconductor, Macronix International Co. Ltd..

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Source: Electronics Newsweekly


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