News Column

Patent Application Titled "Method for Protecting a Gate Structure during Contact Formation" Published Online

May 7, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors CHANG, Hong-Dyi (Taipei City, TW); Su, Pei-Chao (Zhudong Town, TW); Thei, Kong-Beng (Pao-Shan Village, TW); Tao, Hun-Jan (Hsin-Chu City, TW); Chuang, Harry-Hak-Lay (Singapore, SG), filed on December 20, 2013, was made available online on April 24, 2014.

No assignee for this patent application has been made.

Reporters obtained the following quote from the background information supplied by the inventors: "The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. Conventional IC processing involves forming one or more contacts to various features of an IC. For example, oftentimes, contact openings are simultaneously formed to areas of a substrate (or wafer) (e.g., doped regions) and gate structures disposed thereover. It has been observed that the traditional processes for forming contact openings to the substrate and gate structures may result in etching portions of the gate structure, such as the gate stack (e.g., a polysilicon and/or gate electrode). This over-etching of the gate structure can lead to undesirable contact resistance and degrade device performance.

"Accordingly, what is needed is a method for manufacturing an integrated circuit device that addresses the above stated issues."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "A semiconductor device and method for manufacturing a semiconductor device is disclosed. In one embodiment, the method includes providing a substrate and forming at least one gate structure over the substrate and forming a plurality of doped regions in the substrate. The method further comprises forming an etch stop layer over the substrate; removing a first portion of the etch stop layer, wherein a second portion of the etch stop layer remains over the plurality of doped regions; forming a hard mask layer over the substrate; and removing a first portion of the hard mask layer, wherein a second portion of the hard mask layer remains over the at least one gate structure. The method can further comprise forming a first contact through the second portion of the hard mask layer to the at least one gate structure, and a second contact through the second portion of the etch stop layer to the plurality of doped regions.

"In one embodiment, the method includes providing a substrate and forming at least one gate structure over the substrate, wherein the at least one gate structure comprises a dummy gate. The method further comprises forming an etch stop layer over the substrate, including over the at least one gate structure; forming a first interlevel dielectric (ILD) layer over the etch stop layer; and performing a chemical mechanical polishing (CMP) process on the first ILD and etch stop layer until a top portion of the at least one gate structure is exposed. The method can further comprise replacing the dummy gate of the at least one gate structure; forming a hard mask layer over the top portion of the at least one gate structure; forming a second ILD layer over the first ILD layer, including over the hard mask layer; and forming one or more contact openings to the at least one gate structure and to the substrate.

"In one embodiment, the semiconductor device includes a substrate having at least one gate structure disposed thereover and a plurality of doped regions disposed therein; a hard mask layer disposed over the at least one gate structure; an etch stop layer disposed over the plurality of doped regiona; a dielectric layer disposed over the hard mask layer and etch stop layer; and one or more contacts, wherein at least one contact extends through the dielectric layer and the hard mask layer to the at least one gate structure, and wherein at least one contact extends through the dielectric layer and the etch stop layer to the plurality of doped regions.

BRIEF DESCRIPTION OF THE DRAWINGS

"The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

"FIG. 1 is a flow chart of a method for fabricating an integrated circuit device according to aspects of the present embodiments; and

"FIGS. 2A-2N are various cross-sectional views of embodiments of an integrated circuit device during various fabrication stages according to the method of FIG. 1."

For more information, see this patent application: CHANG, Hong-Dyi; Su, Pei-Chao; Thei, Kong-Beng; Tao, Hun-Jan; Chuang, Harry-Hak-Lay. Method for Protecting a Gate Structure during Contact Formation. Filed December 20, 2013 and posted April 24, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5872&p=118&f=G&l=50&d=PG01&S1=20140417.PD.&OS=PD/20140417&RS=PD/20140417

Keywords for this news article include: Patents, Electronics, Semiconductor.

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Source: Electronics Newsweekly


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