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Patent Application Titled "High-Voltage Metal-Dielectric-Semiconductor Device and Method of the Same" Published Online

May 7, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventors Lee, Ming-Cheng (Hsinchu County, TW); Tsao, Wei-Li (Hsinchu County, TW), filed on December 26, 2013, was made available online on April 24, 2014.

The assignee for this patent application is Mediatek Inc.

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates to a high-voltage device structure. More particularly, the present invention relates to a high-voltage metal-dielectric-semiconductor device structure with improved time dependent dielectric breakdown (TDDB) characteristic and reduced hot carrier injection (HCI) effect.

"High-voltage metal-dielectric-semiconductors are devices for use under high voltages, which may be, but not limited to, voltages higher than the voltage supplied to the I/O circuit. High-voltage metal-dielectric-semiconductor devices may function as switches and are broadly utilized in audio output drivers, CPU power supplies, power management systems, AC/DC converters, LCD or plasma television drivers, automobile electronic components, PC peripheral devices, small DC motor controllers, and other consumer electronic devices.

"FIG. 1 is a schematic, cross-sectional view of a conventional high-voltage N-type metal-dielectric-semiconductor device. As shown in FIG. 1, the high-voltage N-type metal-dielectric-semiconductor device 101 includes a gate 210 overlying an area of a P type substrate 100, a deep N well (DNW) 110 formed in the substrate 100, an N well 120 formed in the substrate 100 proximate a first edge 210a of the gate 210 and doped with a first concentration of an N type dopant, and a channel region 130 doped with a first concentration of a P type dopant underlying a portion of the gate 210 adjacent the N well 120.

"Shallow trench isolation (STI) region 160 is formed in the first portion of the N well 120. An N.sup.+ tap region 150 is adjacent to the second portion of the N well 120 distal from the first edge 210a of the gate 210. An N type source region 155 including an N.sup.+ region and an N type lightly doped region 155b is formed in the P well 140 proximate a second edge 210b of the gate 210 opposite to the first edge 210a.

"The N.sup.+ tap region 150 is formed between the STI region 160 and the STI region 162. The N.sup.+ tap region 150 is not self-aligned with the gate 210 but is separated from the gate 210 by a distance D. The above-described high-voltage N-type metal-dielectric-semiconductor device 101 utilizes STI region 160 to drop drain voltage and makes high drain sustained voltage. Besides, the above-described high-voltage N-type metal-dielectric-semiconductor device 101 uses well implant to form drain terminal. The above-described high-voltage N-type metal-dielectric-semiconductor device 101 occupies a large surface area on a chip because of the offset STI region. Further, the driving current of such device may be insufficient.

"It is desirable to provide a high-voltage metal-dielectric-semiconductor device that can sustain at least 5V at the drain terminal based on a 2.5V device process or below. It is also desirable to provide a high-voltage metal-dielectric-semiconductor device based on a 2.5V device process or below, which is CMOS-compatible and occupies relatively smaller chip real estate. It is also desirable to provide a high-voltage metal-dielectric-semiconductor device based on a 2.5V device process or below, which has increased driving current."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "It is one objective of the invention to provide a high-voltage metal-dielectric-semiconductor device based on 2.5V process or below, which can sustain at least 5V at the drain terminal.

"It is yet another objective of the invention to provide a high-voltage metal-dielectric-semiconductor device based on 2.5V process or below, which is CMOS-compatible and occupies relatively smaller chip real estate.

"To these ends, according to one aspect of the present invention, there is provided a high-voltage metal-dielectric-semiconductor transistor including a semiconductor substrate; a trench isolation region in the semiconductor substrate surrounding an active area; a gate overlying the active area; a drain doping region of a first conductivity type in the active area; a source doping region of the first conductivity type in a first well of a second conductivity type in the active area; and a source lightly doped region of the first conductivity type between the gate and the source doping region; wherein no isolation is formed between the gate and the drain doping region.

"From another aspect of the invention, a high-voltage metal-dielectric-semiconductor transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate surrounding an active area; a gate overlying the active area; a drain doping region of a first conductivity type in a bulk portion of the semiconductor substrate, wherein the semiconductor substrate is of a second conductivity type; a drain lightly doped region of the first conductivity type in the bulk portion of the semiconductor substrate between the gate and the drain doping region; a source doping region of the first conductivity type in a well of the second conductivity type; and a source lightly doped region of the first conductivity type between the gate and the source doping region; wherein no isolation is formed between the gate and the drain doping region.

"From still another aspect of the invention, a high-voltage metal-dielectric-semiconductor transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate surrounding an active area; a gate overlying the active area; a drain doping region of a first conductivity type in a first well of the first conductivity type, wherein no isolation is formed within the first well, the semiconductor substrate is of a second conductivity type; a source doping region of the first conductivity type in a second well of the second conductivity type; and a source lightly doped region of the first conductivity type between the gate and the source doping region.

"These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a schematic, cross-sectional diagram illustrating a conventional high-voltage N-type metal-dielectric-semiconductor device.

"FIG. 2 is an exemplary layout of the improved high-voltage N-type metal-dielectric-semiconductor transistor structure in accordance with one embodiment of this invention.

"FIG. 3 is a schematic, cross-sectional view taken alone line I-I' of FIG. 2.

"FIG. 4 is a schematic, cross-sectional diagram showing a high-voltage N-type metal-dielectric-semiconductor transistor structure in accordance with another embodiment of this invention.

"FIG. 5 is a schematic, cross-sectional diagram showing a high-voltage N-type metal-dielectric-semiconductor transistor structure in accordance with yet another embodiment of this invention.

"FIG. 6 illustrates a variant of the high-voltage N-type metal-dielectric-semiconductor transistor structure of FIG. 5.

"FIG. 7 is a schematic, cross-sectional diagram showing a high-voltage N-type metal-dielectric-semiconductor transistor structure in accordance with yet another embodiment of this invention.

"FIG. 8 is a variant of the high-voltage N-type metal-dielectric-semiconductor transistor structure of FIG. 7."

For more information, see this patent application: Lee, Ming-Cheng; Tsao, Wei-Li. High-Voltage Metal-Dielectric-Semiconductor Device and Method of the Same. Filed December 26, 2013 and posted April 24, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=5846&p=117&f=G&l=50&d=PG01&S1=20140417.PD.&OS=PD/20140417&RS=PD/20140417

Keywords for this news article include: Electronics, High Voltage, Mediatek Inc., Semiconductor.

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Source: Electronics Newsweekly