News Column

Memoir Systems Introduces Renaissance Memory Uptime for SOCs

April 29, 2014

Memoir Systems Inc. on April 21 introduced Renaissance Memory Uptime IP, a solution that protects against the growing threat of catastrophic memory failure due to multi-bit errors.

According to a release, the high performance SOCs at the heart of data center equipment are integrated and often have hundreds of megabits of embedded memory. In an industry that targets 99.999 percent system uptime, OEMs succeed or fail based on their ability to deliver reliable products, with no tolerance for system failure due to memory errors.

"The potential for cloud computing in mission critical environments is huge, but it comes with risks-system outages can lead to critical failure and can be costly," said Awais Nemat, founder and CEO at PLUMgrid, a Cloud Networking start-up. "With many enterprise applications as well as mission critical medical, financial, and aeronautic applications moving to the cloud, the stakes have never been higher."

"Premier OEMs do not want to risk their reputations or incur the expensive consequences of system downtime due to catastrophic memory errors," said Sundar Iyer, co-founder and CEO at Memoir. "They need a lightweight solution that protects against multi-bit failures during runtime."

The company noted that high end servers and networking equipment use ECC (Error Correction Code) memory protection primarily to correct soft or transient memory errors. However, traditional ECC corrects only single bit errors and is unable to correct multi-bit memory failures. This is a problem, particularly when a hard memory error occurs since a permanent single-bit error renders ECC ineffective against future errors at a given memory word.

Additionally, Renaissance Memory Uptime uses Memoir's Pattern Aware Memory Technology to provide a non-intrusive solution that is transparent to the designer. It exploits the principle that if single bit errors are guaranteed to be detected and corrected proactively within a tightly specified time window during run-time, then the probability of catastrophic memory errors can be proven to be reduced by orders of magnitude over the lifetime of the product.

Renaissance Memory Uptime provides an optimal solution for a variety of configurations, taking into account the memory type, width, depth, clock frequency, mean time to failure and many other design parameters. It is highly parameterized and field programmable. The solution exposes standard single or multi-port SRAM interfaces. It adds negligible gate count, and does not require any software intervention.

For OEMs that need to guarantee high system availability, Renaissance Memory Uptime offers a solution that can reduce system downtime due to memory errors.

Memoir Systems, Inc. is a provider of memory technology that is delivered as Semiconductor Intellectual Property (SIP).

More information:

www.memoir-systems.com.

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