The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "This invention relates generally to the field of semiconductors and, more particularly, to approaches for applying a self-forming barrier layer along bottom surfaces of vias, trenches, or the like.
"The semiconductor integrated circuit (IC) industry has experienced rapid growth in recent years. Specifically, generations of ICs have been produced whereby each generation has smaller and more complex circuits than the previous generation. However, for these advances to be realized, developments in IC processing and manufacturing are needed. Under this course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.
"Semiconductor devices are typically formed using multiple layers of material, including conductive, semi-conductive, dielectric, and insulative layers. To provide electrical conductivity between layers in a semiconductor device, a hole or via may be formed through certain layers. The via is then lined with a barrier layer, such as Ti, TiN, or Ti/TiN, and filled with an electrically conductive material, such as a metal, to provide electrical conductivity between the layers.
"Under previous approaches, multiple surfaces of a via were lined with the barrier layer, and the device was then subject to high temperatures. Unfortunately, barrier layers positioned along a bottom surface of the via often diffuse into the metal layer of the device positioned below the via. Such diffusion has adverse impacts on the reliability of the device."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may then be further processed (e.g., annealed).
"A first aspect of the present invention provides a method for forming a barrier layer in a semiconductor device, comprising: selectively applying the barrier layer along a bottom surface of a via of the semiconductor device; applying a liner layer along a set of sidewalls of the via; and annealing the semiconductor device.
"A second aspect of the present invention provides a method for forming a barrier layer in a semiconductor device, comprising: selectively applying the barrier layer along a bottom surface of a via of the semiconductor device, the via being formed through an ultra low k layer and a cap layer of the semiconductor device; applying a liner layer over the barrier layer and along a set of sidewalls of the via; filling the via with a metal; and processing the semiconductor device to remove the liner layer from over the barrier layer.
"A third aspect of the present invention provides a semiconductor device, comprising: a first metal layer; a cap formed over the first metal layer; an ultra low k layer formed over the cap layer; and a via formed through the ultra low k layer and the cap layer, the via comprising a barrier layer selectively formed along a bottom surface of the via, and a liner layer along a set of sidewall of the via.
BRIEF DESCRIPTION OF THE DRAWINGS
"These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings in which:
"FIGS. 1A-D shows a cross-section view of a semiconductor device during its formation according to an embodiment of the present invention;
"FIGS. 2A-D shows a cross-section view of a semiconductor device during its formation according to an embodiment of the present invention;
"FIGS. 3A-D shows another cross-section view of a semiconductor device during its formation according to an embodiment of the present invention;
"FIGS. 4A-B shows another cross-section view of a semiconductor device during its formation according to an embodiment of the present invention.
"The drawings are not necessarily to scale. The drawings are merely representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting in scope. In the drawings, like numbering represents like elements."
For additional information on this patent application, see: Zhao, Larry; He, Ming; Zhang, Xunyuan; Lin,
Keywords for this news article include: Electronics, Semiconductor,
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