Patent Issued for Methods of Adding Pads and One Or More Interconnect Layers to the Passivated Topside of a Wafer Including Connections to at Least a Portion of the Integrated Circuit Pads Thereon
The patent's inventor is Johnson, Morgan T (
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "Advances in semiconductor manufacturing technology have resulted in, among other things, reducing the cost of sophisticated electronics to the extent that integrated circuits have become ubiquitous in the modern environment.
"As is well-known, integrated circuits are typically manufactured in batches, and these batches usually contain a plurality of semiconductor wafers within and upon which integrated circuits are formed through a variety of semiconductor manufacturing steps, including, for example, depositing, masking, patterning, implanting, etching, and so on.
"Completed wafers are tested to determine which die, or integrated circuits, on the wafer are capable of operating according to predetermined specifications. In this way, integrated circuits that cannot perform as desired are not packaged, or otherwise incorporated into finished products.
"It is common to manufacture integrated circuits on roughly circular semiconductor substrates, or wafers. Further, it is common to form such integrated circuits so that conductive regions disposed on, or close to, the uppermost layers of the integrated circuits are available to act as terminals for connection to various electrical elements disposed in, or on, the lower layers of those integrated circuits. These conductive regions are commonly referred to as pads, or bond pads. During testing, which is often referred to as wafer probing or wafer sorting, the pads are commonly contacted with a probe card. Such wafer probing typically includes mounting the wafer on a moveable chuck that is used to position the wafer relative to a probe card and to hold the wafer in place during testing.
"As the physical dimensions of integrated circuits continue to shrink, the pad size and pad pitch have also been shrinking. Consequently, it has become more difficult and costly to manufacture and maintain probe cards that are capable contacting integrated circuits with small pads with tight pad pitch.
"What is needed are methods and structures for reducing the need for high precision and high maintenance probe cards."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "Briefly, a pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ink pattern provides an electrical pathway between bond pads on an integrated circuit and large contact pads disposed on the topside of the integrated circuit. Each of the large contact pads is much greater in area than the corresponding bond pads, and are spaced apart so that the pitch of the large contact pads is much greater than that of the bond pads.
"In one aspect of the present invention, the conductive ink includes a mixture of conductive particles and wafer bonding thermoset plastic.
"In another aspect of the present invention, the conductive ink is heated and disposed on a wafer by an ink jet printing system."
For the URL and additional information on this patent, see: Johnson, Morgan T. Methods of Adding Pads and One Or More Interconnect Layers to the Passivated Topside of a Wafer Including Connections to at Least a Portion of the Integrated Circuit Pads Thereon. U.S. Patent Number 8697456, filed
Keywords for this news article include: Electronics, Semiconductor,
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