The assignee for this patent application is
Reporters obtained the following quote from the background information supplied by the inventors: "During fabrication of some integrated circuit dies, the dies are exposed to a plasma environment that exposes the dies to very high charges. These charges are harsh and can damage components on the die. For example, during many etching processes, the dies are put into the plasma environment to remove specific layers on the die. Components on the dies, such as transistors, are susceptible to plasma charging or antenna damage when they are exposed to the plasma environment. Damage sustained to a die and/or the components located thereon while a die is located in a plasma environment is referred to as plasma induced damage (PID).
"In the plasma environment, metals connected to the gate oxides (or simply the gates) of transistors act as antennae and build up a charge. More specifically, the gates may be electrically floating during this state of fabrication, so they accumulate charge in the plasma environment. The charge causes a voltage potential to build up across the gate, which in turn causes a tunneling current to flow through the gate during plasma processing. A high level of tunneling current degrades the gate and causes premature failure of the gate and/or the die.
"Currently, an antenna ratio is established during the design of a die in order to determine the areas of the gates and the metals connected to the gates in order to keep the voltage potentials to a constant value or below a constant value. It has been assumed that keeping the voltage potentials to a constant value will reduce damage in the gates due to tunneling. The antenna ratio is proportional to the ratio of the metal area to the gate area, wherein the metal area is the area of metal that is electrically connected to the gate. The antenna ratio is set to be less than a specified value for every individual gate in a specific design. The specified value is calculated by stressing a single transistor design with different antenna ratios. It is assumed that all gates in the die abide by this same charge dissipation rules for a specific antenna ratio. By applying the antenna ratio, the voltage build-up across different gates in the design remains the same.
"One problem with the present use of the antenna ratio is that the failure rate of the gates is not necessarily based on the voltage potential that the antenna ratio seeks to remain constant. Accordingly, the present use of the antenna ratio does not provide an accurate fault prediction of the gates."
In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "Integrated circuit dies and methods of making dies are disclosed. An embodiment of a die includes at least one transistor gate, wherein the gate has an area. A conductor is connected to the gate, wherein the conductor has an area. The area of the conductor is proportional to the area of the gate raised to a power, wherein the power is a function of the failure rate of the gate.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIG. 1 is an isometric view of an embodiment of a portion of a transistor on an integrated circuit in a plasma environment.
"FIG. 2 is a schematic diagram of the transistor of claim 1.
"FIG. 3 is a flowchart describing a method of manufacturing dies based on new antenna ratio rules."
For more information, see this patent application: Jain, Palkesh; Krishnan, Anand T. Integrated Circuit Die and Method of Making. Filed
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