No assignee for this patent application has been made.
Reporters obtained the following quote from the background information supplied by the inventors: "Data is conventionally stored in flash memory in a digital format (i.e., stored as bits). However, an underlying physical media in each memory cell typically exhibits the data as a level of a threshold voltage, which is an analog signal. The threshold voltage is achieved by storing a certain amount of electric charge in a floating gate. The bits are read out by applying a reference voltage to control gates of the memory cells. The bits are sensed by determining whether transistors in the memory cells are switched on or off by the applied reference voltage. Although the threshold voltages fluctuate with many noise factors, such as program/erase cycling, retention and read/write disturbances, if the threshold voltages do not cross a boundary defined by the reference voltage, the stored bits can be correctly read out of the memory. Read error rates increase when the threshold voltages cross the boundary.
"It would be desirable to implement a flash memory read error rate reduction."
In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventors' summary information for this patent application: "The present invention concerns an apparatus having a first circuit and a second circuit. The first circuit may be configured to (i) generate a reference voltage used by a memory circuit in a first read of a set of data and (ii) adjust the reference voltage based on a plurality of parameters to lower an error rate in a second read of the set from the memory circuit. The second circuit may be configured to update the parameters in response to an error correction applied to the set after the first read from the memory circuit. The memory circuit is generally configured to store the data in a nonvolatile condition by adjusting a plurality of threshold voltages.
"The objects, features and advantages of the present invention include providing a method and/or apparatus for implementing a flash memory read error rate reduction that may (i) reduce read error rates, (ii) track channel parameters for multiple data groups, (iii) track the channel parameters without performing extra reads, (iv) operate with flash memory, (v) operate with solid state drives, (vi) adjust a reference voltage used by a memory to read data, (vii) adjust soft-decision decoding to account for channel parameter drifting, (viii) operate with different data group granularity and/or (ix) be implemented in an integrated circuit.
BRIEF DESCRIPTION OF THE DRAWINGS
"These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:
"FIG. 1 is a block diagram of an example apparatus;
"FIG. 2 is a block diagram of an example implementation of a controller in the apparatus in accordance with a preferred embodiment of the present invention;
"FIG. 3 is a graph of example single-level cell threshold voltage distributions;
"FIG. 4 is a graph of shifted single-level cell threshold voltage distributions;
"FIG. 5 is a graph of example multi-level cell threshold voltage distributions; and
"FIG. 6 is a block diagram of an example implementation of a tracking circuit."
For more information, see this patent application: Chen, Zhengang; Wu, Yunxiang. Flash Memory Read Error Rate Reduction. Filed
Keywords for this news article include: Patents.
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