This patent application has not been assigned to a company or institution.
The following quote was obtained by the news editors from the background information supplied by the inventors: "Storage capacity required for semiconductor memory devices such as DRAM (Dynamic Random Access Memory) has been growing year by year. To satisfy the requirement, in recent years, a memory device called multi-chip package has been proposed. In the multi-chip package, a plurality of memory chips are stacked. However, in the case of the multi-chip package, a wire needs to be provided for each chip to connect each memory chip and a package substrate. Therefore, it is difficult to stack many memory chips.
"On the other hand, in recent years, a semiconductor device of a type in which a plurality of memory chips with penetrating electrodes are stacked has been proposed (See Japanese Patent Application Laid-Open No. 2005-136187). In the semiconductor device of the type, among penetrating electrodes provided on each memory chip, the penetrating electrodes that are provided on the same plane position when seen from a stacking direction are electrically short-circuited. Therefore, even if the number of chips stacked increases, the number of electrodes connected to the package substrate does not increase. Thus, it is possible to stack a larger number of memory chips.
"When semiconductor chips with penetrating electrodes are stacked, bump electrodes that are provided on upper and lower chips need to be in accurate contact with each other. Accordingly, compared with an operation of stacking chips in the multi-chip package, more accurate positioning is required.
"However, when the semiconductor chips having the penetrating electrodes are once stacked, connection states of the bump electrodes cannot be visually checked. Accordingly, to evaluate whether a connection failure occurs, a highly accurate load circuit or measurement circuit needs to be mounted on each of the semiconductor chips, which increases the chip area. Furthermore, an evaluation using a load circuit or a measurement circuit mounted on each semiconductor chip requires quite a long time when the number of bump electrodes is large."
In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventor's summary information for this patent application: "In one embodiment, there is provided a method for testing a semiconductor device, the method includes: preparing a first semiconductor chip having a first bump electrode and a first driver circuit that drives the first bump electrode, and a second semiconductor chip having a second bump electrode and a second driver circuit that drives the second bump electrode; staking the first and second semiconductor chips so that the first bump electrode and the second bump electrode are electrically connected to each other to form a current path including the first and second bump electrodes; and driving, in a test mode, the current path to a first potential by the first driver circuit while driving the current path to a second potential different from the first potential by the second driver circuit.
"According to the present invention, a consumption current is purposefully increased by causing a so-called bus fight during a test mode. Therefore, connection states of bump electrodes can be evaluated only by observing a change in the consumption current.
BRIEF DESCRIPTION OF THE DRAWINGS
"FIG. 1 is a schematic cross-sectional view of a semiconductor device of the present invention;
"FIG. 2 is a cross-sectional view of a penetrating electrode TSV;
"FIG. 3 is a schematic diagram for explaining a structure of a bidirectional data bus DB;
"FIG. 4 is a block diagram showing a test circuit provided in a memory chip MC0 shown in FIG. 1;
"FIG. 5 is a block diagram showing a state where a test device is connected to the semiconductor device 10 shown in FIG. 1;
"FIG. 6 is a flowchart for explaining a test method for a semiconductor device according to the present embodiment;
"FIG. 7 is a diagram for explaining a scan operation for driver circuits to output high-level data in turn;
"FIG. 8A is a schematic diagram showing a current path P0 in a case where a memory chip MC0 is selected;
"FIG. 8B is a schematic diagram showing a current path P1 in a case where a memory chip MC1 is selected;
"FIG. 8C is a schematic diagram showing a current path P2 in a case where a memory chip MC2 is selected;
"FIG. 8D is a schematic diagram showing a current path P3 in a case where a memory chip MC3 is selected;
"FIG. 9A is an example of a monitoring result of the consumption current Im by a tester 30 and shows a monitoring result in a case where the memory chip MC0 is selected;
"FIG. 9B is an example of a monitoring result of the consumption current Im by a tester 30 and shows a monitoring result in a case where the memory chip MC1 is selected;
"FIG. 10A is a schematic diagram showing an example in which a bus fight is caused between the memory chip MC0 and the memory chip MC1;
"FIG. 10B is a schematic diagram showing an example in which a bus fight is caused between the memory chip MC1 and the memory chip MC2;
"FIG. 10C is a schematic diagram showing an example in which a bus fight is caused between the memory chip MC2 and the memory chip MC3;
"FIG. 11 is a circuit diagram showing an example in which a limiter circuit 70 is connected to a driver circuit D;
"FIG. 12 is a circuit diagram showing an example in which a loose contact occurring in an address bus AB can be detected; and
"FIG. 13 is a circuit diagram showing an example in which one driver circuit is commonly assigned to a plurality of address buses AB0 to ABm."
URL and more information on this patent application, see: IKEDA, Hiroaki. Test Method for Semiconductor Device Having Stacked Plural Semiconductor Chips. Filed
Keywords for this news article include: Patents, Electronics, Semiconductor.
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