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"Semiconductor Memory Cell Array Having Fast Array Area and Semiconductor Memory Including the Same" in Patent Application Approval Process

February 12, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent application by the inventors YU, Haksoo (Seongnam-si, KR); KIM, Dae-Hyun (Hwaseong-si, KR); KANG, Uksong (Seongnam-si, KR); PARK, Chulwoo (Yongin-si, KR); CHOI, Joosun (Yongin-si, KR); CHOI, Hyojin (Suwon-si, KR), filed on July 17, 2013, was made available online on January 30, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application has not been assigned to a company or institution.

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present disclosure relates to a semiconductor memory, and more particularly, to configuration of a memory cell array of a semiconductor memory.

"The critical dimension (CD) of a volatile semiconductor memory such as a dynamic random access memory (DRAM) may be gradually scaled down according to a demand on high speed, large capacity, and low power.

"Although it is difficult to continue to scale down the critical dimension due to a limit to the resolution of photolithography, improvement on the performance of a memory chip may be continuously desired. Also, a large storage capacity and a low-power characteristic may be desired."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "One embodiment is directed to provide a semiconductor memory cell array which comprises a first memory cell array area including first group memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed; and a second memory cell array area including second group memory cells arranged in the chip in a matrix of rows and columns and having a second operating speed different from the first operating speed, wherein the first and second memory cell array areas are accessed by addressing of a DRAM controller.

"Another embodiment is directed to provide a semiconductor memory cell array which comprises a first memory cell array area including first group memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed; and a second memory cell array area including second group memory cells arranged in the chip in a matrix of rows and columns and having a second operating speed faster than the first operating speed, an input-output sense amplifier being interposed between the first memory cell array area and the second memory cell array area.

"Still another embodiment is directed to provide a dynamic random access memory which comprises a semiconductor memory cell array including a first memory cell array area including first group memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed and a second memory cell array area including second group memory cells arranged in the chip in a matrix of rows and columns and having a second operating speed different from the first operating speed; a decoding unit configured to select rows and columns of the semiconductor memory cell array; and a buffer unit configured to buffer a command, an address, write data, and output data read from the semiconductor memory cell array.

"In still another embodiment, a random access method comprises forming a first memory cell array area including first group memory cells having a first operating speed and a second memory cell array area having a second operating speed faster than the first operating speed; and accessing the first memory cell array area using a low address of a basic address and the second memory cell array area using a high address of the basic address.

"In still another embodiment, a random access method comprises forming a first memory cell array area including first group memory cells having a first operating speed and a second memory cell array area having a second operating speed faster than the first operating speed; and accessing the first memory cell array area using a basic address and the second memory cell array area using an extended address extended from the basis address.

"Still another embodiment is directed to provide a semiconductor memory cell array which comprises a first memory cell array area including first group memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed; and a second memory cell array area including second group memory cells arranged in the chip in a matrix of rows and columns and having a second operating speed faster than the first operating speed, wherein the first memory cell array area and the second memory cell array area are accessed by addressing of a DRAM controller and have different bit line loading from each other.

"In example embodiments, the first memory cell array area and the second memory cell array area share a word line enable signal of a row decoder to have the same bit line loading.

"In example embodiments, the first memory cell array area and the second memory cell array area are connected to separated word lines and have different word line loading.

"In example embodiments, the second memory cell array area is connected with a column repair circuit and is used as a fail address memory to a column fail address for a column repair.

"In example embodiments, the second memory cell array area is connected with a refresh control circuit and is used as a refresh information memory to store refresh strong/weak data for a refresh skip operation.

BRIEF DESCRIPTION OF THE FIGURES

"The above and other objects and features will become apparent from the following description with reference to the following figures, wherein like reference numerals refer to like parts throughout the various figures unless otherwise specified, and wherein:

"FIG. 1 is a block diagram illustrating arrangement of a semiconductor memory cell array according to an embodiment of the inventive concept.

"FIG. 2 is a diagram illustrating a semiconductor memory cell array according to one exemplary embodiment.

"FIG. 3 is a diagram illustrating a semiconductor memory cell array according to another exemplary embodiment.

"FIG. 4 is a diagram illustrating a semiconductor memory cell array according to still another exemplary embodiment.

"FIG. 5 is a diagram illustrating a semiconductor memory cell array according to still another exemplary embodiment.

"FIG. 6 is a diagram illustrating a semiconductor memory cell array according to still another exemplary embodiment.

"FIG. 7 is a diagram illustrating a semiconductor memory cell array according to still another exemplary embodiment.

"FIG. 8 is a block diagram schematically illustrating arrangement of a semiconductor memory cell array according to another exemplary embodiment.

"FIG. 9 is a diagram illustrating an exemplary embodiment of a semiconductor memory cell array in FIG. 8.

"FIG. 10 is a diagram illustrating another exemplary embodiment of a semiconductor memory cell array in FIG. 8.

"FIG. 11 is a diagram illustrating arrangement of word lines of a semiconductor memory cell array in FIG. 1 or 8 according to an exemplary embodiment.

"FIG. 12 is a diagram illustrating arrangement of word lines of a semiconductor memory cell array in FIG. 1 or 8 according to another exemplary embodiment.

"FIG. 13 is a diagram illustrating an embodiment in which a fast array area according to certain exemplary embodiments is applied to a column repair.

"FIG. 14 is a diagram illustrating an embodiment in which a fast array area according to exemplary embodiments is used for refresh control.

"FIG. 15 is a diagram illustrating connection between a memory cell and an input-output sense amplifier applied to FIG. 1 or 8, according to exemplary embodiments.

"FIG. 16 is a diagram illustrating address mapping of a semiconductor memory cell array according to an exemplary embodiment.

"FIG. 17 is a diagram illustrating address mapping of a semiconductor memory cell array according to another exemplary embodiment.

"FIGS. 18A to 18C are diagrams illustrating address mapping of a semiconductor memory cell array according to other exemplary embodiments.

"FIG. 19 is a diagram illustrating an interface of a semiconductor memory according to an exemplary embodiment.

"FIG. 20 is a diagram illustrating an interface of a semiconductor memory according to another exemplary embodiment.

"FIG. 21 is a block diagram schematically illustrating an application of various embodiments applied to a semiconductor memory device.

"FIG. 22 is a block diagram schematically illustrating an application of various embodiments applied to a data processing device.

"FIG. 23 is a block diagram an application of various embodiments applied to a mobile device."

URL and more information on this patent application, see: YU, Haksoo; KIM, Dae-Hyun; KANG, Uksong; PARK, Chulwoo; CHOI, Joosun; CHOI, Hyojin. Semiconductor Memory Cell Array Having Fast Array Area and Semiconductor Memory Including the Same. Filed July 17, 2013 and posted January 30, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=399&p=8&f=G&l=50&d=PG01&S1=20140123.PD.&OS=PD/20140123&RS=PD/20140123

Keywords for this news article include: Patents, Electronics, Semiconductor, Random Access Memory.

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Source: Electronics Newsweekly


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