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"Semiconductor-On-Insulator (Soi) Structure with Selectively Placed Sub-Insulator Layer Void(S) and Method of Forming the Soi Structure" in Patent...

February 12, 2014



"Semiconductor-On-Insulator (Soi) Structure with Selectively Placed Sub-Insulator Layer Void(S) and Method of Forming the Soi Structure" in Patent Application Approval Process

By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent application by the inventors Furukawa, Toshiharu (Essex Junction, VT); Robison, Robert R. (Colchester, VT); Williams, Richard Q. (Essex Junction, VT), filed on September 25, 2013, was made available online on January 30, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to International Business Machines Corporation.

The following quote was obtained by the news editors from the background information supplied by the inventors: "The embodiments of the invention generally relate to semiconductor-on-insulator (SOI) structures and, more specifically, to an SOI structure, such as an SOI field effect transistor (FET), having selectively placed sub-insulator layer void(s) and a method of forming the SOI structure.

"By providing a buried insulator layer between a semiconductor device layer and the semiconductor substrate, semiconductor-on-insulator (SOI) structures minimize parasitic capacitance between devices and the substrate as compared to bulk semiconductor structures. While it may be desirable to minimize capacitance coupling between some devices and the substrate, it may also be desirable to allow strong capacitance coupling between other devices and the substrate. For example, traditional single-gated CMOS devices can benefit from reduced substrate coupling, while double-gated or back-gated CMOS devices can benefit from enhanced substrate coupling, thereby allowing for the substrate to be used as the back gate. Furthermore, while it may be desirable to minimize capacitance coupling between one or more regions of a particular device (e.g., the source diffusion region, the drain diffusion region and/or the body contact diffusion region of an SOI field effect transistor (FET)) and the substrate, it may also be desirable to allow for strong capacitance coupling between another region of the same device (e.g., the channel region of the same SOI FET) and the substrate. This is the case, for example, in low or mixed frequency applications, such as phase locked loops (PLLs), and in other applications where diffusion-to-substrate capacitance is not depleted. Therefore, there is a need in the art for an SOI structure and an associated method of forming the SOI structure that provides for selectively adjusted capacitance coupling between different regions of the semiconductor layer and the substrate."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "Disclosed herein are embodiments of a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. Specifically, the first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. A sub-insulator layer void selectively placed in the substrate below the first device and not below the second device ensures that capacitance coupling between the first device and the substrate will be less than capacitance coupling between the second device and the substrate. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. A sub-insulator layer void selectively placed in the substrate below a first region of a device and not below a second region of the same device ensures that capacitance coupling between the first region and the substrate will be less than capacitance coupling between the second region and the substrate. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source diffusion region, the drain diffusion region and/or the body contact diffusion region, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed herein are embodiments of an associated method of forming such an SOI structure.

"More particularly, disclosed are embodiments of a semiconductor-on-insulator (SOI) structure. This SOI structure can comprise a semiconductor substrate, an insulator layer on the top surface of the semiconductor substrate, and a semiconductor layer on the insulator layer. The semiconductor layer can comprise a first section and a second section positioned laterally adjacent to the first section. Additionally, a void can be positioned within the semiconductor substrate at the top surface such that it is immediately adjacent to the insulator layer and also aligned below the first section. In such an SOI structure, the first section may contain a first device and the second section may contain a second device. Due to the sub-insulator layer void positioned below the first section, but not below the second section, capacitance coupling between the first device and the substrate will be less than capacitance coupling between the second device and the substrate. Alternatively, the first and second sections may comprise first and second regions, respectively, of the same device. Due to a sub-insulator layer void positioned below the first section, but not the second section capacitance coupling between the first region and the substrate will be less than capacitance coupling between the second region and the substrate.

"For example, in one particular embodiment, the SOI structure can comprise an SOI field effect transistor (FET). This SOI FET can comprise a semiconductor substrate, an insulator layer on the top surface of the semiconductor substrate and a semiconductor layer on the insulator layer. The semiconductor layer can comprise source and drain diffusion regions and a channel region positioned laterally between the source and drain diffusion regions. Additionally, voids can be positioned in the semiconductor substrate at the top surface and immediately adjacent to the insulator layer. Furthermore, each one of the voids can be aligned below a corresponding one of the source and drain diffusion regions without extending laterally below the channel region. Since the voids are positioned below the source and drain diffusion regions, but not below the channel region, capacitance coupling between the source and drain diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate.

"Also disclosed herein are embodiments of a method of forming the above-described semiconductor-on-insulator (SOI) structure. The method can comprise forming a semiconductor-on-insulator (SOI) wafer. This SOI wafer can be formed such that it comprises a semiconductor substrate, an insulator layer on the top surface of the semiconductor substrate and a semiconductor layer, comprising a first section positioned laterally adjacent to a second section, on the insulator layer. A void can be formed in the semiconductor substrate and, specifically, at the top surface of the semiconductor substrate immediately adjacent to the insulator layer and aligned below the first section. By forming such a void below the first section but not the second section, capacitance coupling between the first section and the substrate will be less than capacitance coupling between the second section and the substrate.

"The method can also comprise forming a first device in the first section of the semiconductor layer and a second device in the second section of the semiconductor layer. Thus, the sub-insulator layer void selectively placed below the first section, but not the second section, ensures that capacitance coupling between the first device and the substrate will be less than capacitance coupling between the second device and the substrate. Alternatively, the method can also comprise forming first and second regions of the same device within the first and second sections, respectively. Thus, the sub-insulator layer void selectively placed below the first section, but not the second section, ensures that capacitance coupling between the first region and the substrate will be less than capacitance coupling between the second region and the substrate.

"For example, in one particular embodiment, the method of forming an SOI structure can comprise forming an SOI field effect transistor (FET). Specifically, in this embodiment, the method can comprise forming a semiconductor-on-insulator (SOI) wafer. This SOI wafer can be formed such that it comprises a semiconductor substrate, an insulator layer on the top surface of the semiconductor substrate and a semiconductor layer on the insulator layer. The method can further comprising forming, within the semiconductor layer, source and drain diffusion regions and a channel region positioned laterally between the source and drain diffusion regions. Additionally, voids can be formed in the semiconductor substrate at the top surface adjacent to the insulator layer. These voids can be formed such that each one of the voids is aligned below a corresponding one of the source and drain diffusion regions. By forming such voids below the source and drain diffusion regions and not below the channel region, capacitance coupling between the source and drain diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

"The embodiments of the invention will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which:

"FIG. 1 is a cross-section diagram illustrating an embodiment of a semiconductor-on-insulator (SOI) structure;

"FIG. 2A is a cross-section diagram illustrating an embodiment of an SOI field effect transistor (FET);

"FIG. 2B is a different cross-section diagram illustrating the SOI FET from FIG. 2A;

"FIG. 3 is a flow diagram illustrating an embodiment of a method of forming an SOI structure;

"FIG. 4 is a cross-section diagram illustrating a partially completed SOI structure formed according to the method of FIG. 3;

"FIG. 5 is a cross-section diagram illustrating a partially completed SOI structure formed according to the method of FIG. 3;

"FIG. 6 is a cross-section diagram illustrating a partially completed SOI structure formed according to the method of FIG. 3;

"FIG. 7 is a cross-section diagram illustrating a partially completed SOI structure formed according to the method of FIG. 3;

"FIG. 8 is a cross-section diagram illustrating a partially completed SOI structure formed according to the method of FIG. 3;

"FIG. 9 is a flow diagram illustrating an embodiment of a method of forming an SOI FET structure;

"FIG. 10 is a cross-section diagram illustrating a partially completed SOI FET formed according to the method of FIG. 9;

"FIG. 11 is a cross-section diagram illustrating a partially completed SOI FET formed according to the method of FIG. 9;

"FIG. 12A is a cross-section diagram illustrating a partially completed SOI FET formed according to the method of FIG. 9;

"FIG. 12B is a different cross-section diagram illustrating the partially completed SOI FET from FIG. 12A;

"FIG. 13A is a cross-section diagram illustrating a partially completed SOI FET formed according to the method of FIG. 9;

"FIG. 13B is a different cross-section diagram illustrating the partially completed SOI FET from FIG. 13A;

"FIG. 14A is a cross-section diagram illustrating a partially completed SOI FET formed according to the method of FIG. 9;

"FIG. 14B is a different cross-section diagram illustrating the partially completed SOI FET from FIG. 14A;

"FIG. 15A is a cross-section diagram illustrating a partially completed SOI FET formed according to the method of FIG. 9;

"FIG. 15B is a different cross-section diagram illustrating the partially completed SOI FET from FIG. 15A;

"FIG. 16A is a cross-section diagram illustrating a partially completed SOI FET formed according to the method of FIG. 9;

"FIG. 16B is a different cross-section diagram illustrating the partially completed SOI FET from FIG. 16A;

"FIG. 17A is a cross-section diagram illustrating a partially completed SOI FET formed according to the method of FIG. 9;

"FIG. 17B is a different cross-section diagram illustrating the partially completed SOI FET from FIG. 17A;

"FIG. 18A is a cross-section diagram illustrating a partially completed SOI FET formed according to the method of FIG. 9; and

"FIG. 18B is a different cross-section diagram illustrating the partially completed SOI FET from FIG. 18A."

URL and more information on this patent application, see: Furukawa, Toshiharu; Robison, Robert R.; Williams, Richard Q. Semiconductor-On-Insulator (Soi) Structure with Selectively Placed Sub-Insulator Layer Void(S) and Method of Forming the Soi Structure. Filed September 25, 2013 and posted January 30, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4729&p=95&f=G&l=50&d=PG01&S1=20140123.PD.&OS=PD/20140123&RS=PD/20140123

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

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Source: Electronics Newsweekly


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