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Researchers Submit Patent Application, "Semiconductor Devices Having E-Fuse Structures and Methods of Fabricating the Same", for Approval

February 12, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventor KIM, Deok-Kee (Yongin-si, KR), filed on September 23, 2013, was made available online on January 30, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "Example embodiments relate to semiconductor devices and methods of fabricating the same.

"Semiconductor devices have been identified as a relatively important factor in the electronics industry because of their relatively small size, multifunctionality, and relatively low manufacturing costs. Semiconductor devices may serve as storage devices for storing logic data or as logic devices for processing logic data.

"Some conventional semiconductor devices include a fuse structure capable of performing various functions. However, fabricating and/or programming conventional fuse structures is relatively difficult.

"Moreover, as the electronics industry becomes more highly developed, semiconductor devices including fuse structures may require increased integration, and requirements for fuse structures may become more widely varied."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventor's summary information for this patent application: "Example embodiments relate to semiconductor devices including e-fuse structures and methods of fabricating the same.

"At least some example embodiments provide semiconductor devices including e-fuse structures capable of increasing integration, and methods of fabricating the same.

"At least some example embodiments also provide semiconductor devices including e-fuse structures capable of improving program efficiency, and methods for fabricating the same.

"At least one example embodiment of inventive concepts provides a semiconductor device including: an e-fuse gate crossing over an e-fuse active portion defined in a substrate; a floating pattern including a first portion between the e-fuse gate and the e-fuse active portion, and at least a pair of second portions extending upward along sidewalls of the e-fuse gate from both edges of the first portion; a blocking dielectric pattern between the floating pattern and the e-fuse gate; and an e-fuse dielectric layer between the floating pattern and the e-fuse active portion.

"According to at least some example embodiments, the floating pattern may include a metallic conductive material having a work function different from that of the e-fuse gate.

"Top surfaces of the second portions of the floating pattern may be coplanar or substantially coplanar with a top surface of the e-fuse gate. Alternatively, top surfaces of the second portions of the floating pattern may be disposed at a height lower than a top surface of the e-fuse gate.

"The substrate may have a first region, a second region, and a third region that are separated from one another. The e-fuse active portion may be defined in the first region. In this example, the semiconductor device may further include: a first MOS gate dielectric layer and a first MOS gate sequentially stacked on a first MOS active portion defined in the second region of the substrate; and a second MOS gate dielectric layer and a second MOS gate sequentially stacked on a second MOS active portion defined in the third region of the substrate. A work function of the first MOS gate may be different from that of the second MOS gate.

"The first MOS gate may include a first sub-gate, a second sub-gate and a third sub-gate that are sequentially stacked. The work function of the first MOS gate may be a first coupling-work function generated by coupling the first, second and third sub-gates of the first MOS gate. The second MOS gate may include a first sub-gate and a second sub-gate that are sequentially stacked. The work function of the second MOS gate may be a second coupling-work function generated by coupling of the first and second sub-gates of the second MOS gate.

"The first sub-gate of the first MOS gate may have a work function different from the second coupling-work function, the floating pattern may have the same or substantially the same work function as that of the first sub-gate of the first MOS gate, and a work function of the e-fuse gate may be the same or substantially the same as the second coupling-work function.

"The e-fuse gate may include a first sub-gate and a second sub-gate. The first sub-gate of the e-fuse gate, the first and second sub-gates of the first MOS gate, and the first sub-gate of the second MOS gate may serve as diffusion barriers with respect to corresponding metal elements.

"The floating pattern may be formed of the same or substantially the same material as the first sub-gate of the first MOS gate. The second sub-gate of the first MOS gate may be formed of the same or substantially the same material as that of the first sub-gate of the second MOS gate. The third sub-gate of the first MOS gate may be formed of the same or substantially the same material as the second sub-gates of the second MOS gate. The e-fuse gate may be formed of the same or substantially the same material as the second MOS gate.

"The first sub-gate of the first MOS gate may be thicker than the first sub-gate of the second MOS gate.

"The first and second sub-gates of the first MOS gate may cover a bottom surface and sidewalls of the third sub-gate of the first MOS gate. The first sub-gate of the second MOS gate may cover a bottom surface and sidewalls of the second sub-gate of the second MOS gate.

"According to at least some example embodiments, a semiconductor device may further include a mold layer disposed on the substrate. In this example, the e-fuse gate, the blocking dielectric pattern and the floating pattern may be disposed in a first groove defined in a portion of the mold layer corresponding to the first region. The first MOS gate may be disposed in a second groove defined in a portion of the mold layer corresponding to the second region. The second MOS gate may be disposed in a third groove defined in portion of the mold layer corresponding to the third region.

"According to at least some example embodiments, the semiconductor device may further include: a first insulation spacer between the second portion of the floating pattern and the mold layer; a second insulation spacer between the sidewall of the first MOS gate and the mold layer; and a third insulation spacer between the sidewall of the second MOS gate and the mold layer. An inner sidewall of the first groove, an inner sidewall of the second groove, and an inner sidewall of the third groove may be defined by the first insulation spacer, the second insulation spacer, and the third insulation spacer, respectively. A horizontal distance between outer sidewalls of the pair of the second portions of the floating pattern may be larger than a width of the first MOS gate.

"According to at least some example embodiments, the semiconductor device may further include: an e-fuse source/drain formed in the e-fuse active portion at sides of the floating pattern; a first MOS source/drain formed in the first MOS active portion at sides of the first MOS gate; and a second MOS source/drain formed in the second MOS active portion at sides of the second MOS gate. One of the first MOS source/drain and the second MOS source/drain may be doped with an N-type dopant, whereas the other may be doped with a P-type dopant. The e-fuse source/drain may be doped with the same type of dopant as that of one of the first MOS source/drain and the second MOS source/drain.

"The e-fuse dielectric layer may include a high-k dielectric material having a dielectric constant higher than that of a silicon oxide layer.

"At least one other example embodiment provides a method of fabricating a semiconductor device including: defining an e-fuse active portion by forming a device isolation pattern on a substrate; forming a mold layer on the substrate, the mold layer including a first groove crossing the e-fuse active portion; sequentially stacking a floating pattern, a blocking dielectric pattern, and an e-fuse gate in the first groove; and forming an e-fuse dielectric layer between the e-fuse active portion and the floating pattern. The floating pattern includes a first portion formed on the e-fuse active portion and at least a pair of second portions extending upward along sidewalls of the e-fuse gate from edges of the first portion.

"According to at least some example embodiments, the substrate may include a first region, a second region, and a third region separated from each other. The first groove may be disposed in the first region, and the device isolation pattern may further define a first MOS active portion in the second region and a second MOS active portion in the third region. The mold layer may further include a second groove in the second region and a third groove in the third region. In this example, the method may further include: forming a first MOS gate in the second groove; forming a first MOS gate dielectric layer between the first MOS gate and the first MOS active portion; forming a second MOS gate in the third groove; and forming a second MOS gate dielectric layer between the second MOS gate and the second MOS active portion.

"According to at least some example embodiments, the forming of the first, second and third grooves may include: sequentially stacking an e-fuse dielectric layer and a first dummy gate on the e-fuse active portion; sequentially stacking a first MOS gate dielectric layer and a second dummy gate on the first MOS active portion; sequentially stacking a second MOS gate dielectric layer and a third dummy gate on the second MOS active portion; forming a mold layer over the substrate; planarizing the mold layer to expose the first, second and third dummy gates; and forming the first, second and third grooves by removing the first to third dummy gates.

"According to at least some example embodiments, prior to forming the mold layer, an e-fuse source/drain may be formed in the e-fuse active portion at each side of the first dummy gate; a first MOS source/drain may be formed in the first MOS active portion at each side of the second dummy gate; and a second MOS source/drain may be formed in the second MOS active portion at each side of the third dummy gate.

"According to at least some example embodiments, prior to forming the mold layer, a first insulation spacer may be formed on sidewalls of the first dummy gate, a second insulation spacer may be formed on sidewalls of the second dummy gate, and a third insulation spacer may be formed on sidewalls of the third dummy gate.

"According to at least some example embodiments, the floating pattern, the blocking dielectric pattern, the e-fuse gate, the first MOS gate, and the second MOS gate may be formed by: forming (e.g., conformally forming) a first conductive layer on the substrate including the first, second and third grooves; removing portions of the first conductive layer such that the first conductive layer is disposed on an inner surface of the first groove on the e-fuse active portion; forming (e.g., conformally forming) a blocking dielectric layer on the substrate; removing the blocking dielectric layer and the first conductive layer in the third region; exposing the first conductive layer in the second region by removing the blocking dielectric layer in the second region; forming (e.g., conformally forming) a second conductive layer on the substrate, the blocking dielectric layer in the first region, the exposed first conductive layer in the second region, and an inner surface of the third groove; forming a third conductive layer filling the first, second and third grooves on the second conductive layer; and planarizing the third conductive layer, the second conductive layer, the blocking dielectric layer, and the first conductive layer to expose the mold layer.

"According to at least some example embodiments, a first coupling-work function generated by coupling of the first, second and third conductive layers in the second region may be different from a second coupling-work function generated by coupling of the second and third conductive layers in the third region. The first conductive layer may be thicker than the second conductive layer. A work function of the first conductive layer may be different from a coupling-work function generated by coupling the second and third conductive layers.

"Prior to planarizing, top surfaces of the second portions of the floating pattern may be recessed such that the top surfaces of the second portions are disposed at a height lower than a top surface of the e-fuse gate.

"A width of the first groove may be larger than a width of the second groove.

"At least one other example embodiment provides an e-fuse structure for a semiconductor device including: an e-fuse gate formed on an e-fuse active portion of a substrate; and a floating layer pattern formed between the e-fuse active portion of the substrate and the e-fuse gate. The floating layer pattern covers a lower surface and sidewalls of the e-fuse gate.

"According to at least some example embodiments, a blocking dielectric pattern may be arranged between the floating layer pattern and the e-fuse gate; and an e-fuse dielectric layer may be arranged between the floating layer pattern and the e-fuse active portion of the substrate. An e-fuse dielectric layer may be formed between the floating layer pattern and the e-fuse active portion of the substrate. Spacers may be formed at the sidewalls of the floating layer pattern. An upper surface of portions of the floating layer pattern covering the sidewalls of the e-fuse gate may be substantially co-planar with an upper surface of the e-fuse gate. Alternatively, an upper surface of portions of the floating layer pattern covering the sidewalls of the e-fuse gate may be recessed relative to an upper surface of the e-fuse gate. Source and drain regions may be formed in the substrate at each side of the e-fuse active portion.

"At least one other example embodiment provides an e-fuse structure for a semiconductor device. According to at least this example embodiment, the e-fuse structure includes: an e-fuse gate formed on an e-fuse active portion of a substrate; and a metallic conductive layer pattern formed between the e-fuse active portion of the substrate and the e-fuse gate. The metallic conductive layer pattern covers a lower surface and sidewalls of the e-fuse gate and is insulated from the e-fuse active portion and the e-fuse gate.

"According to at least some example embodiments, a blocking dielectric pattern may be arranged between the metallic conductive layer pattern and the e-fuse gate; and an e-fuse dielectric layer may be arranged between the metallic conductive layer pattern and the e-fuse active portion of the substrate. An e-fuse dielectric layer may be formed between the metallic conductive layer pattern and the e-fuse active portion of the substrate. Spacers may be formed at the sidewalls of the metallic conductive layer pattern. An upper surface of portions of the metallic conductive layer pattern covering the sidewalls of the e-fuse gate may be substantially co-planar with an upper surface of the e-fuse gate. Alternatively, an upper surface of portions of the metallic conductive layer pattern covering the sidewalls of the e-fuse gate may be recessed relative to an upper surface of the e-fuse gate. Source and drain regions may be formed in the substrate at each side of the e-fuse active portion.

BRIEF DESCRIPTION OF THE DRAWINGS

"The accompanying drawings are included to provide a further understanding of the example embodiments of inventive concepts, and are incorporated in and constitute a part of this specification. The drawings illustrate example embodiments and, together with the description, serve to explain principles of inventive concepts. In the drawings:

"FIG. 1 is a planar view illustrating a semiconductor device according to an example embodiment of inventive concepts;

"FIG. 2 is a cross-sectional view illustrating the semiconductor device of FIG. 1 sectioned along Ia-Ia', Ib-Ib', II-II', and III-III';

"FIG. 3 is a cross-sectional view illustrating an example modification of the semiconductor device shown in FIG. 1 sectioned along Ia-Ia', Ib-Ib', II-II', and III-III';

"FIGS. 4A to 11A are planar views for explaining a method of fabricating a semiconductor device according to an example embodiment of inventive concepts; and

"FIGS. 4B to 11B are cross-sectional views along Ia-Ia', Ib-Ib', II-II', and III-III' shown in FIGS. 4A to 11A."

For additional information on this patent application, see: KIM, Deok-Kee. Semiconductor Devices Having E-Fuse Structures and Methods of Fabricating the Same. Filed September 23, 2013 and posted January 30, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4697&p=94&f=G&l=50&d=PG01&S1=20140123.PD.&OS=PD/20140123&RS=PD/20140123

Keywords for this news article include: Patents, Electronics, Semiconductor.

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Source: Electronics Newsweekly


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