The patent's assignee is
News editors obtained the following quote from the background information supplied by the inventors: "Luminescence diode chips are known wherein a mirror layer is arranged between a semiconductor body having an active region provided for generating radiation and a carrier element, said minor layer being provided for reflecting radiation generated in the active region and thus for increasing the radiation power emitted overall. However, it has been found that degradation can occur in such semiconductor chips, for example, on account of oxidation of the minor layer or upon the action of moisture on the semiconductor chip."
As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Embodiments of the present invention specify a semiconductor chip which has an improved aging stability and a reduced sensitivity toward moisture. Further embodiments of the invention specify a method by which efficient optoelectronic semiconductor chips can be produced in a simple and reliable manner.
"In accordance with an embodiment, an optoelectronic semiconductor chip comprises a semiconductor body and a carrier, on which the semiconductor body is arranged. The semiconductor body has an active region, preferably provided for generating or for receiving radiation. The active region is arranged between a first semiconductor layer of a first conduction type and a second semiconductor layer of a second conduction type, which differs from the first conduction type. The first semiconductor layer is arranged on that side of the active region which faces the carrier. The first semiconductor layer is electrically conductively connected to a first connection layer, which is arranged between the carrier and the semiconductor body and preferably directly adjoins the first semiconductor layer. An encapsulation layer is arranged between the first connection layer and the carrier. In a plan view of the semiconductor chip, the encapsulation layer projects at least in regions beyond a side face that delimits the semiconductor body.
"By means of the encapsulation layer, the first connection layer, which is preferably embodied as a minor layer for the radiation to be generated or to be received in the active region, is decoupled from the surroundings. It can prevent air or moisture from penetrating into the first connection layer. Furthermore, the encapsulation layer can suppress migration of material of the first connection layer, for example silver.
"The encapsulation layer preferably covers those regions of a main face of the semiconductor body facing the carrier in which the main face is not covered by the first connection layer. Particularly preferably, said regions are completely covered by the encapsulation layer, wherein the encapsulation layer furthermore preferably directly adjoins the main face.
"In a preferred configuration, the encapsulation layer runs fully circumferentially around the semiconductor body in plan view, that is to say along the entire circumference of the semiconductor body. The encapsulation layer furthermore preferably adjoins the first semiconductor layer fully circumferentially along the side face of the semiconductor body. By means of the configuration projecting beyond the semiconductor body, the encapsulation layer is embodied in such a way that the main face of the semiconductor body is completely covered by the encapsulation layer even in the case of slight alignment deviations during production along the side faces of the semiconductor body.
"In other words, the semiconductor body, in a plan view of the semiconductor chip, is preferably arranged completely within an outer boundary of the encapsulation layer.
"In a further preferred configuration, a main extension plane of a region of the encapsulation layer that projects beyond the side face of the semiconductor body runs parallel to a main extension plane of the active region. In other words, the encapsulation layer continues beyond the side face of the semiconductor body in a planar fashion or in a substantially planar fashion. The side face of the semiconductor body is therefore free of material of the encapsulation layer.
"In a further preferred configuration, an outer boundary of the first connection layer, in a plan view of the semiconductor chip, runs completely within the semiconductor body. Therefore, the first connection layer does not project beyond the semiconductor body at any location. Protection of the first connection layer against external environmental influences can thus be realized in a simplified manner.
"In a further preferred configuration, the encapsulation layer is embodied in a metallic fashion. The encapsulation layer is furthermore preferably embodied in a multilayered fashion. Particularly preferably, the encapsulation layer comprises a gold layer.
"The first connection layer preferably contains silver or consists of silver. Silver is distinguished by a particularly high reflectivity in the visible spectral range. Alternatively or supplementarily, the first connection layer can contain a different material having a high reflectivity, for example aluminum or palladium.
"In a further preferred configuration, the encapsulation layer completely covers the first connection layer on the side facing away from the semiconductor body. The encapsulation layer furthermore preferably directly adjoins the first connection layer.
"In one preferred configuration, the semiconductor body has at least one recess which extends from the carrier through the active region. The second semiconductor layer is preferably electrically conductively connected to a second connection layer in the recess.
"The first connection layer is preferably arranged in regions between the semiconductor body and the second connection layer.
"In order to avoid an electrical short circuit, a first insulation layer is preferably arranged between the first connection layer and the second connection layer, in particular, between the encapsulation layer and the second connection layer. The encapsulation layer is preferably embodied in such a way that the first insulation layer does not adjoin the first main face of the semiconductor body. In other words, the first insulation layer is spaced apart from the carrier at every location of the main face in a direction running perpendicularly toward the main face and toward the carrier.
"In a method for producing a plurality of optoelectronic semiconductor chips, a semiconductor layer on a substrate is provided, wherein the semiconductor layer has an active region arranged between a first semiconductor layer of a first conduction type and a second semiconductor layer of a second conduction type, which differs from the first conduction type. A first connection layer is formed on the semiconductor layer sequence. An encapsulation layer is formed on the first connection layer. A composite assembly comprising the semiconductor layer sequence and a carrier is formed. A plurality of semiconductor bodies are formed from the semiconductor layer sequence, wherein the encapsulation layer is exposed in regions. The composite assembly is singulated into a plurality of semiconductor chips.
"The method steps are preferably carried out in the order of the above enumeration. However, at least with regard to individual steps, other sequences can also be expedient.
"The semiconductor bodies are preferably formed in such a way that the side faces arising in the course of forming the semiconductor bodies, in a plan view of the semiconductor layer sequence, lie completely within an outer boundary of the encapsulation.
"In a preferred configuration, a growth substrate for the semiconductor layer sequence is removed. This is preferably done after the composite assembly has been formed. The carrier serves in particular for mechanically stabilizing the semiconductor layer sequence, such that the growth substrate is no longer required for this purpose.
"The method described is particularly suitable for producing a semiconductor chip described further above. Therefore, features explained in connection with the semiconductor chip can also be used for the method, and vice versa.
BRIEF DESCRIPTION OF THE DRAWINGS
"Further features, configurations and expediences will become apparent from the following description of the exemplary embodiments in conjunction with the figures.
"FIGS. 1A and 1B show an exemplary embodiment of a semiconductor chip in schematic plan view (FIG. 1A) and associated sectional view (FIG. 1B) along the line AA'; and
"FIGS. 2A to 2F show an exemplary embodiment of a method for producing a plurality of optoelectronic semiconductor chips.
"Elements that are identical, of identical type or act identically are provided with the same reference signs in the figures.
"The figures and the size relationships of the elements illustrated in the figures among one another should not be regarded as to scale. Rather, individual elements may be illustrated with an exaggerated size in order to enable better illustration and/or in order to afford a better understanding."
For additional information on this patent application, see: Engl,
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