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Researchers Submit Patent Application, "Methods and Apparatuses for Interconnect Tracing", for Approval

February 13, 2014



By a News Reporter-Staff News Editor at Computer Weekly News -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Richter, Andre Oliver (Muenchen, DE); Reinig, Helmut (Isen, DE); Todorov, Vladimir (Muenchen, DE), filed on July 20, 2012, was made available online on January 30, 2014.

The patent's assignee is Intel Mobile Communications Gmbh.

News editors obtained the following quote from the background information supplied by the inventors: "A trace monitor helps embedded software developers to debug software that has been written for a system on chip (SoC). A SoC is an integrated circuit that incorporates typical computer components, such as central processing units (CPUs), graphic processing units (GPUs) and memory controllers in a single silicon die. These components communicate with each other over on-chip interconnects. For embedded software developers, it might be helpful to observe the software-caused communications as they propagate through the interconnects. This may provide information, such as transferred data words between CPU and memory, which can be used for debugging.

"The process of capturing signal values for later observation is called tracing and the captured data is called the trace-data. The entity performing the observations is usually described as a trace monitor. Depending on the type of interconnects, trace monitors may hook up to either a bus or to one or more ports of a crossbar switch.

"A trace monitor should never become an active member of the interconnects. It should always stay invisible for other components in order to comply with the paradigm of non-intrusive tracing. In a multitude of scenarios, the interplay of the different parties on the bus may be the cause of a bug. To take a single example, two components may be engaged in a race condition, because both want to interact with the same memory location at the same time. Altering these race conditions, e.g. due to a trace monitor that utilizes the same bus to transmit its trace data, may cause the bug to disappear.

"Generally, SoC protocols are distinguishable from one another by vendor and their intended use-case and performance. Some of the most sophisticated and widespread interconnect protocols are: the ARM AMBA (Advanced Microcontroller Bus Architecture) protocol family; the IBM Core Connect protocol family; and the Open Core Protocol (OCP).

"Many solutions employ IDLE cycle filtering as a trace-size reduction technique. If a trace solution offers advanced trace-size reduction techniques, such as signal compression and abstraction, it is only available for the AHB protocol. Unfortunately, AHB is considered only a mid-performance protocol, which disqualifies these solutions for use in high-performance SoCs that use faster protocols. On the other hand, if a solution supports high-performance protocols, it offers only IDLE cycle filtering and no further, advanced trace-size reduction techniques.

"Therefore, it would be advantageous to have a method, system, and computer program product that addresses one or more of the issues discussed above."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "A method of tracing in a system on chip is provided. The method comprising; tracing an exchange of a plurality of signals between a master device and a slave device of the system on chip, wherein the plurality of signals have a number of requests and a number of responses; and tracking the number of requests and the number of responses made before and after tracing is activated to determine which Reponses of the number of responses to trace after tracing is activated and a remaining number of responses to trace after tracing is deactivated.

"An apparatus is provided. The apparatus includes a trace monitor configured to trace an exchange of a plurality of signals between a master device and a slave device of the system on chip, wherein the plurality of signals have a number of requests and a number of responses; and track the number of requests and the number of responses made before and after tracing is activated to determine which Reponses of the number of responses to trace after tracing is activated and a remaining number of responses to trace after tracing is deactivated.

"Logic encoded in one or more non-transitory computer readable media is provided that includes code for execution and when executed by a processor is operable to perform operations comprising: tracing an exchange of a plurality of signals between a master device and a slave device of the system on chip, wherein the plurality of signals have a number of requests and a number of responses; and tracking the number of requests and the number of responses made before and after tracing is activated to determine which Reponses of the number of responses to trace after tracing is activated and a remaining number of responses to trace after tracing is deactivated.

BRIEF DESCRIPTION OF DRAWINGS

"In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale. In the following description, aspects of this disclosure are described with reference to the following drawings, in which:

"FIG. 1 is an illustration of a system on chip in accordance with an aspect of this disclosure;

"FIG. 2 is an illustration of an incorrect assignment in accordance with an aspect of this disclosure;

"FIG. 3 is an illustration of context-awareness and user-adjustable transaction filtering in accordance with an aspect of this disclosure;

"FIG. 4 is a block diagram of the hardware architecture of the trace monitor in accordance with an aspect of this disclosure;

"FIG. 5 is an illustration of a trace action signal in accordance with an aspect of this disclosure;

"FIG. 6 is an illustration of a REQ captured signal in accordance with an aspect of this disclosure;

"FIG. 7 is an illustration of a trace action signal in accordance with an aspect of this disclosure;

"FIG. 8 is a flowchart for identifying network congestion in a system on chip in accordance with an aspect of this disclosure;

"FIG. 9 is a flowchart for identifying network congestion in a system on chip with counters in accordance with an aspect of this disclosure;

"FIG. 10 is a flowchart for identifying network congestion in a system on chip with counters in accordance with an aspect of this disclosure;

"FIG. 11 is a flowchart for identifying network congestion in a system on chip with FIFO in accordance with an aspect of this disclosure; and

"FIG. 12 is a flowchart for identifying network congestion in a system on chip with FIFO in accordance with an aspect of this disclosure."

For additional information on this patent application, see: Richter, Andre Oliver; Reinig, Helmut; Todorov, Vladimir. Methods and Apparatuses for Interconnect Tracing. Filed July 20, 2012 and posted January 30, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=153&p=4&f=G&l=50&d=PG01&S1=20140123.PD.&OS=PD/20140123&RS=PD/20140123

Keywords for this news article include: Software, Intel Mobile Communications Gmbh.

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Source: Computer Weekly News


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