This patent application is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to a phase interpolating apparatus and associated phase interpolating method, and more particularly, to a phase interpolating apparatus and method capable of predicting interpolation and switching phase to be interpolated in advanced.
"A phase interpolating apparatus is widely used in modern electronics because it is used to generate multiple clock signals having different phases based on few clock signals. Please refer to FIG. 1, which illustrates a block diagram of a phase interpolating apparatus 100 in the prior art. As shown in FIG. 1, the phase interpolating apparatus 100 in the prior art comprises a phase interpolator 101 and multiplexers (denoted as Mux in abbreviation) 103 and 105. The multiplexer 103 is used to receive input clock signals CLK.sub.0, CLK.sub.2, CLK.sub.4, and CLK.sub.6 having different even phases P.sub.0, P.sub.2, P.sub.4, and P.sub.6, respectively, and is also used to select one of the inputs to the phase interpolator 101. Similarly, the multiplexer 105 is used to receive input clock signals CLK.sub.1, CLK.sub.3, CLK.sub.5, and CLK.sub.7 having different odd phases P.sub.1, P.sub.3, P.sub.5, and P.sub.7, respectively, and is also used to select one of the inputs to the phase interpolator 101. The phase interpolator 101 is used to generate an interpolated clock signal CIS according to the received clock signals.
"However, when a traditional phase interpolating apparatus switches clock signals to be interpolated, an unexpected voltage pulse is sometimes generated. Please refer to FIG. 2, which depicts a diagram for explaining how voltage pulse is generated in the prior art. In the example shown in FIG. 2, the phase interpolating apparatus 100 generates the interpolated clock signal CIS based on the clock signal CLK.sub.0 having phase Po at the upper side and the clock signal CLK.sub.1 having phase P.sub.1 at the lower side at first. Then the phase interpolating apparatus 100 switches to the clock signal CLK.sub.2 from the clock signal CLK.sub.0 to generate the interpolated clock signal CIS with the clock signal CLK.sub.1. As shown in FIG. 2(a), the interpolated clock signal CIS at timing points T.sub.1, T.sub.2, T.sub.3, and T.sub.4 are interpolated according to the clock signals CLK.sub.0 and CLK.sub.1 at the same timing points T.sub.1, T.sub.2, T.sub.3, and T.sub.4.
"As shown in FIG. 2(b), at the moment that the clock signal at the upper side to be interpolated is switched from the clock signal CLK.sub.0 having phase P.sub.0 to the clock signal CLK.sub.2 having phase P.sub.2, a temporary transition state is generated because of the switch transition. In this temporary transition state, value of the clock signal CLK.sub.0 would be residuary and cause the interpolated clock signal CIS to display error. For example, at the timing point T.sub.2 shown in FIG. 2(b), the voltage level of the clock signal CLK.sub.2 is low and so is the clock signal CLK.sub.1, the voltage level of the interpolated clock signal CIS should be low accordingly. But the clock signal CLK.sub.0 is residuary (represented by dashed line). Moreover, the voltage level of the clock signal CLK.sub.0 at timing point T.sub.2 is high. Therefore a voltage pulse P would be interpolated as the interpolated clock signal CIS at timing point T.sub.2. Even though value of the interpolated clock signal CIS is correct after timing point T.sub.2, the voltage pulse P effects accuracy overall. Please refer to FIG. 2©, the upper input signal is switched to the clock signal CLK.sub.2 after timing point T.sub.2, correct values of interpolated clock signal can be read at timing points T.sub.3 and T.sub.4. However, the voltage pulse P which appeared at the timing point T.sub.2 cause un-recoverable errors. Such errors make the interpolated clock signal display un-normal surge or decays, so the waveform becomes incorrect.
"In order to solve the above problem, several solutions were already provided in the prior art. One of these solutions is to wait a predetermined time interval after the switch, and then generate the interpolated clock signal. However, the processing speed is slower in this configuration, and more complicated logic circuits are needed to control the switch and the interpolation separately."
In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventor's summary information for this patent application: "One of objectives of the present invention is to provide a phase interpolating apparatus and a phase interpolating method preventing voltage pulse problems in the prior art.
"An embodiment of the present invention discloses a phase interpolating apparatus comprising: a first signal generation circuit, configured for generating a first signal having a first phase; an optional second signal generation circuit, configured for generating a second signal having the first phase; a third signal generation circuit, configured for generating a third signal having a second phase; a fourth/fifth signal generation circuit, configured for generating a fourth signal having a third phase at a first mode and for generating a fifth signal having the second phase instead of the fourth signal at a second mode; and a phase interpolator, configured for generating an interpolated signal without utilizing the fourth signal operating in the first mode and for generating the interpolated signal according to the first signal, the third signal, and the fifth signal operating in the second mode.
"Based on the aforementioned embodiment, a corresponding phase interpolating method can be concluded accordingly. Since the steps of the phase interpolating method are also derived from the embodiment above, no further description is elaborated here.
"According to the described embodiments, switching input signals in advance according to a prediction result of the next phase to be interpolated is embodied to prevent voltage pulse problems experienced in the prior art and to maintain processing speed. Also, sharing multiplexers and phase interpolating modules enable circuit area to be saved accordingly.
"The above description is only an outline of the technical schemes of the present invention detailed below. Preferred embodiments of the present invention are provided below in conjunction with the attached drawings to enable one with ordinary skill in the art to better understand said and other objectives, features and advantages of the present invention and to make the present invention accordingly.
BRIEF DESCRIPTION OF THE DRAWINGS
"The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
"FIG. 1 illustrates a block diagram of a phase interpolating apparatus in the prior art.
"FIG. 2 depicts a diagram explaining how a voltage pulse is generated in the prior art.
"FIG. 3 shows a block diagram of a phase interpolating apparatus in accordance with an embodiment of the present invention.
"FIGS. 4A and 4B illustrate an exemplary logic circuit structure of the phase interpolator shown in FIG. 3.
"FIG. 5 shows an operating diagram of a phase interpolating apparatus according to one embodiment of the present invention.
"FIG. 6 depicts a diagram of phase sequence of clock signal for generating the interpolated clock signal.
"FIG. 7 illustrates a flowchart diagram of a phase interpolating method in accordance with an embodiment of the present invention."
URL and more information on this patent application, see: Weng, Meng-Tse. Phase Interpolating Apparatus and Method. Filed
Keywords for this news article include: Electronics,
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