The assignee for this patent, patent number 8637953, is
Reporters obtained the following quote from the background information supplied by the inventors: "The stacking of integrated circuits and discrete devices in three dimensions enables advanced
"Directly bonding two silicon wafers face to face and selectively grinding and etching one to leave a transferred device layer is an option that does not involve processing of thermally dissimilar materials. In the device or circuit alignment procedure, however, this technique does not allow direct viewing of alignment patterns and through wafer imaging using infrared light is often used to see through each Si wafer during the alignment procedure. Transfer of device layers from donor substrates to transparent 'handle' substrates allows direct optical alignment of patterns, but introduces pattern shifts and yield limitations as a result of unmatched thermal characteristics and substrate flatness variations.
"Three-dimensional integrated circuit fabrication techniques also often suffer from process induced pattern specific voiding at the bonding surface. Such voiding is often very difficult to control and reduces product yields.
"Therefore a need exists to overcome the problems with the prior art as discussed above."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "In accordance with one aspect of the present invention, a method for fabricating three-dimensional integrated circuits includes etching a crystalline substrate within an area of a substrate side of a donor semiconductor wafer, the substrate side having a substrate thickness and being located opposite a device side of the donor semiconductor wafer, to remove at least a substantial portion of the crystalline substrate within the area. The method further including supporting the donor semiconductor wafer with a supporting structure. The supporting structure allowing flexing of the donor semiconductor wafer within at least a portion of the area after the etching.
"In accordance with another aspect of the present invention, a three-dimensional integrated circuit fabrication apparatus includes an etching tool adapted to etch crystalline substrate within an area of a substrate side of a donor semiconductor wafer. The substrate side has a substrate thickness and is located opposite a device side of the donor semiconductor wafer. The etching tool removes at least a substantial portion of the crystalline substrate within the area. The three-dimensional integrated circuit fabrication apparatus further includes a supporting structure adapted to support the donor semiconductor wafer. The supporting structure allowing flexing of the donor semiconductor wafer within at least a portion of the area after the etching.
"In accordance with another aspect of the present invention, a three-dimensional integrated semiconductor device includes at least a portion of an acceptor wafer comprising a first device layer and at least a portion of a donor wafer with a second device layer bonded to the first device layer. The donor wafer has a crystalline substrate that has been substantially removed from the at least a portion of the donor wafer prior to being bonded to the first device layer, thereby allowing the second device layer to flexibly conform to the first device layer."
For more information, see this patent: La Tulipe, Jr.,
Keywords for this news article include: Electronics, Semiconductor,
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