The patent's assignee for patent number 8638611 is
News editors obtained the following quote from the background information supplied by the inventors: "A semiconductor memory device is a memory device which is fabricated using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), and the like. Semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices. The volatile memory devices may lose stored contents at power-off. The volatile memory devices include a static
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "Integrated circuit memory devices according to embodiments of the invention include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is also provided. The control circuit is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST). The driving of the vertical channel regions is performed concurrently with electrically floating ground and string selection lines (GSL, SSL) within the plurality of vertically-stacked strings of nonvolatile memory cells during at least a second portion of the erase time interval. The driving of the vertical channel regions may be performed by driving the underlying substrate with the erase voltage, which is transferred to the vertical channel regions by the electrical coupling between the substrate and the channel regions.
"According to some embodiments of the invention, the control circuit includes an erase voltage generator, which is configured to generate the erase voltage as a monotonically increasing voltage during the erase time interval. In particular, the erase voltage generator may be configured to generate the erase voltage as a monotonically increasing voltage that is repeatedly stepped-up during multiple time intervals within the erase time interval. The erase voltage generator may include a totem-pole arrangement of transistors, which are configured as diodes. According to additional embodiments of the invention, the erase voltage generator includes a charge pump and a ramping circuit, which is configured to generate the erase voltage by sequentially tapping intermediate nodes of the totem-pole arrangement of transistors having different voltage levels. The ramping circuit may also include a timing control circuit, which is configured to generate a sequence of ramping enable signals during the erase time interval. These ramping enable signals may include respective pulses having leading edges (e.g., low-to-high signal transitions) that are spaced-apart relative to each other at respective time points within the erase time interval.
"According to still further embodiments of the invention, the control circuit may be configured to drive a plurality of word lines within the plurality of vertically-stacked strings of nonvolatile memory cells with a voltage having a magnitude less than the first voltage level, during the erase time interval. In particular, the control circuit may be configured to drive the ground and string selection lines and the plurality of word lines with a ground reference voltage during a first portion of the erase time interval, which precedes the second portion of the erase time interval."
For additional information on this patent, see: Sim, Jaesung; Choi, Jungdal. Vertical Nonvolatile Memory Devices and Methods of Operating Same. U.S. Patent Number 8638611, filed
Keywords for this news article include: Semiconductor,
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