The patent's assignee for patent number 8637923 is
News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a metal-oxide semiconductor field effect transistor (MOSFET) having a recess channel.
"A typical semiconductor device has adopted an individual device, such as a MOSFET device, as a switching device. Accordingly, the size of the MOSFET device has decreased as the semiconductor device becomes highly integrated. As a result, in the MOSFET device having a horizontal channel, which is a typical structure, normal operations have become difficult to perform because of a short channel effect (SCE) and a drain induced barrier lower (DIBL) effect derived from the reduced channel length between a source and a drain.
"Thus, a MOSFET device having a recess channel (hereinafter referred to as a recess transistor) has been introduced to overcome the limitation of the MOSFET device having the horizontal channel. The recess transistor includes a structure in which a gate is filled in a trench formed in an active region of a substrate. Such recess transistor can reduce the SCE and the DIBL effect by lengthening the channel length even if the scale of integration increases in the device.
"FIG. 1 illustrates a cross-sectional view of a typical recess transistor. A cross-sectional view of a double diffused metal-oxide semiconductor (DMOS) is illustrated herein as an example for convenience of description.
"The typical DMOS device includes a doped N.sup.+ substrate (drain) 10, an N-epitaxial layer 11 doped at a lower concentration than the substrate 10, a gate electrode 13 comprising a conductive polysilicon layer filled in a trench, a gate oxide layer 12 formed to a uniform thickness on an inner surface of the trench below the gate electrode 13, an N.sup.+ doped source region 14 formed on both upper sides of the gate electrode 13, and a planarized P-well 15 formed below the N.sup.+ doped source region 14. Also, a source metal layer 16 formed to cover the N.sup.+ doped source region 14 and a dielectric layer 17 formed below the source metal layer 16 to cover the gate electrode 13 are further included. Reference denotation `T1` refers to a thickness `T1` of a portion of the gate oxide layer 12 formed at a bottom portion of the trench.
"However, a gate capacitance may increase in the typical DMOS device because the gate oxide layer 12 is form to a small uniform thickness on inner sidewalls and a bottom surface of the trench. Accordingly, there are limitations in improving a switching speed of the DMOS device functioning as a switching device."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventor's summary information for this patent: "Embodiments of the present invention are directed to provide a recess transistor and a method for fabricating the same, which can improve a switching speed of a device by reducing a gate capacitance.
"In accordance with an aspect of the present invention, there is provided a transistor, including: a substrate including a trench; an insulation layer filled in a portion of the trench, the insulation layer having a greater thickness over an edge portion of a bottom surface of the trench than over a middle portion of the bottom surface of the trench; a gate insulation layer formed over inner sidewalls of the trench, the gate insulation layer having a thickness smaller than the insulation layer; and a gate electrode filled in the trench.
"In accordance with another aspect of the present invention, there is provided a transistor, including: a substrate including a trench; an insulation layer filled in a portion of the trench, the insulation layer having a V shape; a gate insulation layer formed over inner sidewalls of the trench, the gate insulation layer having a thickness smaller than the insulation layer; and a gate electrode filled in the trench.
"In accordance with still another aspect of the present invention, there is provided a method for fabricating a transistor, including: forming a trench in a substrate; forming a polysilicon layer over the substrate and filled in the trench; etching the polysilicon layer in a manner that a portion of the polysilicon layer having a greater thickness over an edge portion of a bottom surface of the trench than over a middle portion of the bottom surface of the trench remains in the trench; oxidizing the remaining portion of the polysilicon layer to form an insulation layer over the bottom surface of the trench and forming a gate insulation layer over inner sidewalls of the trench to a smaller thickness than the insulation layer at substantially the same time; and forming a gate electrode over the insulation layer and filled in the trench."
For additional information on this patent, see: Cho, Cheol-Ho. Transistor Having Recess Channel and Fabricating Method. U.S. Patent Number 8637923, filed
Keywords for this news article include: Electronics,
Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC
Most Popular Stories
- Koch Brothers Step up Anti-Obamacare Campaign
- Obama Administration Releases Proposal to Regulate For-Profit Colleges
- Elizabeth Vargas' Husband Marc Cohn Addresses Rumors
- Keurig Adds Peet's coffee, Alters Starbucks deal
- Quiznos Files for Chapter 11
- U.S. to Relinquish Gov't Control Over Internet
- Vybz Kartel Convicted of Murder
- FDIC Sues Big Banks Over Rate Manipulation
- SoCalGas Reaches Record Spend on Diversity Suppliers
- U.S. Consumer Sentiment Falls in Early March