The patent's inventors are Haufe, Christian (Dresden, DE); Pika, Jens (Bautzen, DE); Winkler, Jorg (Ullersdorf, DE).
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "Semiconductor devices, fabrication processes for manufacturing semiconductor devices, and associated test circuits and test structures are well known. On-chip test architectures are often used to check certain characteristics of a semiconductor device (such as a device that implements combinatorial or sequential logic) manufactured by a particular process. In this regard, the on-chip test structure is fabricated using the proposed manufacturing process, and with standard circuit modules, cell libraries, and the like. Consequently, the on-chip test structure can be exposed to controlled test conditions (e.g., temperature, radiation, electromagnetic interference) to determine how other devices fabricated in accordance with the same process technology might react to the same conditions.
"Exposure of integrated circuits to nuclear radiation can trigger soft errors (radiation-induced misbehavior). Radiation-induced soft errors are usually categorized as single event transients (SETs) or single event upsets (SEUs). An SET represents a transient change in bit state, while an SEU represents a relatively persistent change in bit state. One conventional soft error detection scheme uses random access memory structures to measure the critical amount of charge needed to flip a bit (Qcrit). Another known technique uses flip-flop chains to measure Qcrit. Existing approaches, however, utilize different test structures or test devices to measure SETs and SEUs. Consequently, such existing solutions are inefficient and costly.
"Accordingly, it is desirable to have an efficient and effective semiconductor-based test structure that can detect both SETs and SEUs. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "An exemplary embodiment of a soft error rate (SER) detector circuit is presented herein. The SER detector circuit includes a plurality of detector arrays coupled in series, where each detector array has a plurality of SER test structures coupled in series. Each of the SER test structures includes a plurality of detector elements coupled in series, and each of the SER test structures is configured to detect single event transients (SETs) in a first operating mode and single event upsets (SEUs) in a second operating mode. The SER detector circuit also includes control logic elements to control operation of the plurality of detector arrays.
"Also provided is an exemplary embodiment of an SER detector circuit fabricated on a semiconductor substrate in accordance with a semiconductor fabrication process. The SER detector circuit includes a combined SER test structure configured to detect both SETs and SEUs. The SER detector circuit has a persistent output state for detection of SETs.
"An exemplary embodiment of an SER test structure is also presented. The SER test structure includes a detector chain having an input and an output, and an edge detector having an input and an output. The input of the edge detector is coupled to the output of the detector chain. The edge detector distinguishes non-recordable signal transitions from the detector chain from recordable signal transitions that are indicative of SETs. The SER test structure also includes a capture/hold element having an input and an output. The input of the capture/hold element is coupled to the output of the edge detector. The capture/hold element changes state in response to the edge detector detecting a recordable signal transition that is indicative of a SET, and the capture/hold element retains its state until reset. The SER test structure also includes a counter having an input and an output. The input of the counter is coupled to the output of the capture/hold element, and the counter maintains a count associated with detection of SETs.
"This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter."
For the URL and additional information on this patent, see: Haufe, Christian; Pika, Jens; Winkler, Jorg. Soft Error Rate Detector. U.S. Patent Number 8639992, filed
Keywords for this news article include: Electronics, Semiconductor,
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