The patent's inventors are Li, Ying (
This patent was filed on
From the background information supplied by the inventors, news correspondents obtained the following quote: "The present disclosure generally relates to semiconductor devices, and particularly to semiconductor structures having a dielectric metal oxide spacer configured to enable a self-aligned contact, and methods of manufacturing the same.
"Self-aligned contact structures employ a dielectric spacer around a gate stack, which is sufficiently resistant to etch chemistry employed to form a via hole extending to a surface located below the topmost surface of the gate stack. The material employed for the dielectric spacer has to be different from the dielectric material layer through which the via hole is formed. However, etch chemistries do not provide infinite selectivity. Thus, erosion of some portion of the dielectric spacer is inevitable if any surface of the dielectric spacer is exposed during the formation of the via hole in the dielectric material layer.
"A successful implementation of a self-aligned contact scheme depends on providing sufficient selectivity in the etch process employed to etch the dielectric material layer relative to the material of the dielectric spacer. Typically, doped or undoped silicate glass or organosilicate glass is employed for the dielectric material layer, and silicon nitride is employed for the dielectric spacer. The selectivity of the currently available etch processes is not sufficient to maintain the undesirable etching to the dielectric spacer at an insignificant level. An excessive erosion of the dielectric spacer during formation of a self-aligned via hole can expose a conductive material within a gate stack to cause a direct electrical short, or can form a thin region in the eroded dielectric spacer that provides a leakage current path between a conductive material within a gate stack and a contact via through the thin region. Thus, without a reliable process that minimizes thinning of the dielectric spacer during a self-aligned via hole etch, a self-aligned contact scheme is prone to manufacturing a high percentage of defective devices that do not function or does not meet the specification from the beginning or unreliable devices that fail in time after some usage."
Supplementing the background information on this patent, VerticalNews reporters also obtained the inventors' summary information for this patent: "A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. At least one upper contact-level dielectric material layer is deposited over the lower contact-level dielectric material layer and the dielectric metal oxide spacer, and at least one via hole extending from the topmost surface of the at least one upper contact-level dielectric material layer to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure.
"According to an aspect of the present disclosure, a semiconductor structure includes: a gate dielectric located on a semiconductor substrate; a gate electrode structure located on the gate dielectric; and a dielectric metal oxide spacer contacting an upper portion of the gate electrode and not contacting a lower portion of the gate electrode.
"According to another aspect of the present disclosure, a method of forming a semiconductor structure includes: forming a gate stack on a semiconductor substrate; forming a dielectric liner over the gate stack and the semiconductor substrate; forming a dielectric material layer over the dielectric liner and planarizing the dielectric material layer; recessing an upper portion of the dielectric liner and forms a recessed region laterally surrounding an upper portion of the gate stack; and forming a dielectric metal oxide spacer within the recessed region."
For the URL and additional information on this patent, see: Li, Ying; Utomo,
Keywords for this news article include: Electronics, Semiconductor,
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