Patent number 8637389 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "The invention generally relates to a method of making a semiconductor device, and more particularly, to a method of making semiconductor pillar structures.
"Devices made from semiconductor materials are used to create memory circuits in electrical components and systems. Memory circuits are the backbone of such devices as data and instruction sets are stored therein. Maximizing the number of memory elements per unit area on such circuits minimizes their cost and thus is a primary motivation in the designing of such circuits.
"As the dimensions for structures formed on a semiconductor wafer diminish, tools currently available to create these devices reach their limits. By way of example, currently available 193 nanometer immersion tools will fail to create structures with a pitch of less than about 80 nm. To fabricate features smaller than this with the currently available tools, one must use more complicated processes. One such process is the technique of double exposure/double patterning. Another is the use of sidewall spacers, formed on a template pattern which is then removed. The sidewall spacers are then used as mask during etching of the underlying film or films.
"For simple, one-dimensional, regular line-and-space patterns, both of these techniques have the effect of dividing the photolithographically-produced pitch by two. In this way, the resolution capability of a given photolithography tool can be extended.
"However, for a two-dimensional pattern of regularly-spaced pillars, the double-patterning scheme extends the pitch by a factor of the square root of 2. The sidewall spacer method, as-is, cannot be used at all since such a scheme would produce regularly spaced cylindrical annuli, rather than solid pillars."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "A method of making a semiconductor device includes forming a layer over a substrate, forming a plurality of spaced apart features of imagable material over the layer, forming sidewall spacers on the plurality of features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the layer using the first feature, the filler feature and the second feature as a mask.
"A method of making a nonvolatile memory device array includes forming a plurality of bottom electrodes over a substrate, forming a device layer comprising over the plurality of bottom electrodes, forming a hard mask stack over the device layer, and forming a plurality of photoresist spaced apart features over the hard mask stack.
"The method also includes forming sidewall spacers on the plurality of photoresist spaced apart features, forming a plurality of photoresist filler features between the plurality of photoresist spaced apart features such that upper portions of the sidewall spacers are exposed and such that the plurality of photoresist filler features are located between the sidewall spacers, and removing the sidewall spacers to leave the plurality of photoresist spaced apart features and the plurality of photoresist filler features spaced apart from each other.
"The method also includes etching the hard mask stack using the plurality of photoresist spaced apart features and the plurality of photoresist filler features as a mask, to form a plurality of hard mask features, etching the device layer using the plurality of hard mask features as a mask, to form a plurality of pillar shaped nonvolatile memory cells, and forming a plurality of upper electrodes contacting the plurality of nonvolatile memory cells."
URL and more information on this patent, see: Chen, Yung-Tin; Radigan, Steven J.. Resist Feature and Removable Spacer Pitch Doubling Patterning Method for Pillar Structures. U.S. Patent Number 8637389, filed
Keywords for this news article include: Electronics, Semiconductor,
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