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Patent Issued for Reducing Write Amplification in a Cache with Flash Memory Used as a Write Cache

February 13, 2014



By a News Reporter-Staff News Editor at Computer Weekly News -- A patent by the inventors Belluomini, Wendy A. (San Jose, CA); Gill, Binny S. (San Jose, CA); Ko, Michael A. (San Jose, CA), filed on January 15, 2013, was published online on January 28, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8639883 is assigned to International Business Machines Corporation (Armonk, NY).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Embodiments of the invention relate to memory devices, and in particular, to reducing write amplification in a cache with flash memory used as a write cache.

"A cache is a small, high-speed memory device interposed between a processor and a larger but slower device, such as main memory or storage. Caches temporarily store data that are frequently accessed by applications executing on a processor. Data typically reside in a cache after an initial access to data from main memory or storage. Subsequent accesses to the same data are made to the cache. A cache allows for the data to be accessed in a shorter amount of time by reducing the number of wait states during data accesses.

"Flash memory is a type of non-volatile memory that has low power and high-density. In particular, flash memory is a type of Electrically Erasable Programmable Read Only Memory (EEPROM) device that can be electrically erased and reprogrammed in blocks. Flash memory has features of the Random Access Memory (RAM) because data are rewritable on flash memory. Flash memory also has features of Read Only Memory (ROM) because flash memory devices are non-volatile. Memory cells are arranged in blocks for erasure, and after a block has been erased, the block is available to be reprogrammed. Flash memory has become an increasingly popular form of non-volatile memory because of the flash memory's small size, fast access speeds, shock resistance, and light weight.

"Write amplification is a process that occurs when data are written to solid-state memory arrays. A memory array scans for free space in the memory array, when data are written to the array. Free space in a memory array includes individual cells, pages, and/or blocks of memory cells that are not programmed. Data are written to free space in the memory array, if there is enough free space to write the data. The data in a memory array is rearranged, if there is not enough free space in one location. Data in a memory array is rearranged by erasing, moving, and rewriting the data to a new location within the same memory array. Garbage collection is the process of identifying blocks with valid data for erasure and relocation.

"Write amplification is the process of rearranging old data in a memory array. Rearrangement of data leaves free space for new data that is to be written in the memory array. The amount of write operations memory arrays must do in order to write new data are amplified based upon the amount of free space in the memory array and the size of the new data that is to be written on the memory array. Write amplification can be reduced by an increase in the amount of space on a memory array designated as free space, because less data will have to be rearranged. Performance of flash memory degrades, as a substitute or a supplement to DRAM in a cache, as a result of write amplification because write locations are random in typical caching environments."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "Preferred embodiments of the invention relate to reducing write amplification in a cache with flash memory used as a write cache. An aspect of the invention is a cache. The cache includes a buffer that buffers data to be cached and data to be destaged from cache to a storage subsystem. The cache further includes at least one flash memory device coupled to the buffer. The at least one flash memory device comprises a plurality of logical partitions. Each of the plurality of logical partitions is a logical subdivision of one of the at least one flash memory device and comprises a plurality of pages. The at least one flash memory device caches the data to be cached from the buffer. The cached data in the buffer and a location of the cached data within the plurality of logical partitions are accessible by a processor.

"Another aspect of the invention includes a method for reducing write amplification in a cache with flash memory used as a write cache. The method includes partitioning at least one flash memory device in a cache into a plurality of logical partitions. Each of the plurality of logical partitions is a logical subdivision of one of the at least one flash memory device and comprises a plurality of pages. The method further includes buffering data in a buffer. The buffer buffers data to be cached and data to be destaged from the cache to a storage subsystem. The method further includes writing the data to be cached from the buffer to the at least one flash memory device. The method further includes providing a processor coupled to the buffer with access to the data written to the at least one flash memory device from the buffer and a location of the data written to the at least one flash memory device within the plurality of logical partitions. The method further includes destaging the data written to the at least one flash memory device from the buffer to the storage subsystem.

"Another aspect of the invention includes a computer program product for reducing write amplification in a cache with flash memory used as a write cache. The computer program product includes a computer readable storage medium having computer readable program code embodied therewith. The computer readable program code includes computer readable program code to partition at least one flash memory device in a cache into a plurality of logical partitions. Each of the plurality of logical partitions is a logical subdivision of one of the at least one flash memory device and comprises a plurality of pages. The computer readable program code further includes computer readable program code to buffer data in a buffer. The data buffered is data to be cached and data to be destaged from the cache to a storage subsystem. The computer readable program code further includes computer readable program code to write the data to be cached from the buffer to a flash memory device. The computer readable program code further includes computer readable program code to provide a processor coupled to the buffer with access to the data written to the at least one flash memory device from the buffer and with a location of the data written to the at least one flash memory device within the plurality of logical partitions. The computer readable program code further includes computer readable program code to destage the data from the at least one flash memory device to the storage subsystem.

"These and other, features, aspects, and advantages of the present invention will be apparent with reference to the following detailed description and appended claims."

URL and more information on this patent, see: Belluomini, Wendy A.; Gill, Binny S.; Ko, Michael A.. Reducing Write Amplification in a Cache with Flash Memory Used as a Write Cache. U.S. Patent Number 8639883, filed January 15, 2013, and published online on January 28, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=16&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=800&f=G&l=50&co1=AND&d=PTXT&s1=20140128.PD.&OS=ISD/20140128&RS=ISD/20140128

Keywords for this news article include: International Business Machines Corporation.

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Source: Computer Weekly News


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