News Column

Patent Issued for Processing Unit, Chip, Computing Device and Method for Accelerating Data Transmission

February 12, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Chang, Xiao Tao (Beijing, CN); Hou, Rui (Beijing, CN); Liu, Wei (Beijing, CN); Wang, Kun (Beijing, CN); Zhang, Yu (Beijing, CN), filed on March 29, 2011, was published online on January 28, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8639840 is assigned to International Business Machines Corporation (Armonk, NY).

The following quote was obtained by the news editors from the background information supplied by the inventors: "Currently, a processing unit within a chip can be composed of processor cores or be composed of hardware accelerators (accelerator for short). Improving processing capability of processor core by means of an accelerator is one of the trends in manufacturing high performance CPU. An accelerator can assist a processor core in processing some specialized tasks such as encryption, compression, etc. The adoption of an accelerator relieves the burden of a processor core which can mainly perform general purpose tasks that barely have any rule in structure. A chip with an accelerator generally has enhanced computing capability, because it not only possesses flexibility of general purpose processor, but also has a computing advantage of special purpose hardware.

"Referring to FIG. 1A or FIG. 1B, a processing unit usually will broadcast a data request on a bus, and the requested data can be stored in a cache coupled to a processor core or merely be stored in memory. Normally, the requested data will be searched for in the cache first, and corresponding data will be read from relatively low-speed memory only if there is no desired data in the cache. Data provided in the memory will probably be simultaneously loaded in the cache so that subsequent read for same data will all be performed in the cache without having to access the memory again.

"Referring to FIG. 2A, after the processing unit broadcasts a data request on the bus, both the cache and the memory will query its local storage and send a reply signal to the processing unit for telling whether it has any hit data block(s), and the processing unit will accordingly make preparation for receiving hit data block(s). The request for data and the reply thereto constitute a handshake. If there is a hit data block, one data block will be transmitted from the cache or memory to the processing unit after each handshake. The processing unit will then initiate a next round of handshakes after obtaining certain data block so as to request a next data block. In other words, the processing unit needs to initiate a handshake once at every request for data block, so sixteen handshakes have to be initiated for requesting sixteen data blocks."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "Since an accelerator is commonly used for doing some specialized tasks, most of the data it requests for processing are streaming data. Streaming data is characterized by having a large volume of data, data blocks having a continuous address and having the requested data blocks located in a same cache. Furthermore, in some scenarios, data requested by a processor core can also constitute streaming data.

"Since a handshake will be conducted multiple times, there are many defects in the existing process of an accelerator requesting data for processing. First, multiple handshakes can lead to an increase in power consumption of the chip. Each time a data request is sent, all the caches on the chip that are in a listening state need to perform an address matching process for determining whether there is cache hit. Therefore, repeatedly performing address matching will greatly increase power consumption of the whole chip. Second, multiple handshakes can result in unnecessary latency. Each time a data request is received, the cache needs to perform address matching, thereby consuming more time periods, leading to more handshakes and longer latency. The same problem will occur when a processor core requests streaming data in a non-local cache or memory.

"In order to save power consumption of a system and reduce transmission latency, the present invention, by utilizing characteristics of streaming data, creatively proposes a transmission mode in which a plurality of data blocks are transmitted via one handshake. The present invention employs a handshake save policy. When a processing unit sends a request including a plurality of data blocks (usually in unit of cacheline) on a bus, a cache or memory will perform address matching to judge whether there is any hit data block. If there is any hit data block, the cache or memory only needs to reply once and then start to continuously transmit the hit data blocks it possesses. Thus, a separate handshake for each data block is no longer needed.

"The invention provides a processing unit for accelerating data transmission, the processing unit being coupled to a bus, including: a transmission policy controller for controlling initiation of a handshake save policy according to predetermined applicable condition, the handshake save policy being used to allow data blocks of at least two adjacent address segments to be continuously transmitted on the bus; and a data access controller for sending data request on the bus, receiving reply to the data request from the bus, and receiving hit data block from the bus if there is any hit data block.

"The invention also provides a chip for accelerating data transmission, including the above processing unit and a bus.

"The invention also provides a computing device for accelerating data transmission, including: the above chip and a memory.

"The invention also provides a method for accelerating data transmission, including: controlling initiation of a handshake save policy according to predetermined applicable condition, the handshake save policy being used to allow data blocks of at least two adjacent address segments to be continuously transmitted on a bus; sending data request on the bus; receiving reply to the data request from the bus; and receiving hit data block transmitted according to the handshake save policy from the bus if there is any hit data block.

"When processing streaming data, the handshake save policy of the present invention can save power consumption of chip and reduce transmission latency, thereby improving work efficiency of overall processing unit."

URL and more information on this patent, see: Chang, Xiao Tao; Hou, Rui; Liu, Wei; Wang, Kun; Zhang, Yu. Processing Unit, Chip, Computing Device and Method for Accelerating Data Transmission. U.S. Patent Number 8639840, filed March 29, 2011, and published online on January 28, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=17&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=843&f=G&l=50&co1=AND&d=PTXT&s1=20140128.PD.&OS=ISD/20140128&RS=ISD/20140128

Keywords for this news article include: Electronics, Data Transmission, International Business Machines Corporation.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Electronics Newsweekly


Story Tools