The assignee for this patent, patent number 8638792, is
Reporters obtained the following quote from the background information supplied by the inventors: "Designing an integrated circuit (IC) or a system usually requires verification and/or debugging to ensure design correctness. One common practice may be based on hardware assisted verification (HAV) which provides visibility for a logic module by cloning the module and piping inputs to the module through a FIFO (First In First Out) delay buffer. U.S. Pat. No. 7,213,216 describes examples of such a practice. Simulation of test cases for the logic module can be performed on the cloned logic module using the buffered inputs. However, if a module contains multiple clocks (or in multiple clock domains), HAV may require all inputs to each clock domain to be buffered in a separate FIFO. As a result, additional hardware and complex software are required to synchronize simulation operations in each clock domain.
"Furthermore, an FIFO implemented in an on-chip RAM (Random Access Memory) may be limited by the availability of unused memory space. To increase the amount of buffering in an FIFO, an off-chip memory, such as DDR2 (Double Data Rate 2) or SDRAM (Synchronous Dynamic RAM), may be employed. However, board real estate and/or pin limitations may prohibit implementing an FIFO using a single physical memory for each clock domain. Thus, multiple FIFOs' for different clock domains may be required to be built from a single physical memory.
"Nevertheless, an off-chip memory may be limited by fixed data widths. In addition, separate address space for each FIFO may have severe bandwidth limitations caused by, for example, significant overhead in memory context switching.
"Therefore, traditional data buffer for hardware assisted design verification does not provide an efficient and scalable solution. Furthermore, background information with respect to logic design or verification can be found in the following U.S. Pat. Nos. 5,036,473; 5,452,231; 5,596,742; 5,661,662; 5,761,484; 5,812,414; and 6,581,191."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventor's summary information for this patent: "An embodiment of the present invention includes methods and apparatuses that compile a representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains. Each source subchannel may generate packets carrying signal data from one of the portions of the source logic. A representation of a destination circuit may be compiled to include one or more destination subchannels associated with portions of destination logic replicating the source logic. Each destination subchannel may forward the signal data via the packets to one of the portions of the destination logic. A switching logic may be configured to map the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels. A single queue may be configured to couple with the switching logic to record packets of a plurality of clock domains from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels. The destination logic may emulate the source logic synchronized with the plurality of clock domains delayed by the delay period.
"In another aspect of the present invention, packets may be generated to carry signal data from a plurality of portions of source logic for a destination logic cloning portions of the source logic. The packets may include identifiers identifying virtual channels mapping the plurality of portions of the source logic to a plurality of portions of the destination logic. A queue may store the packets as a trace of the signal data for a period. The packets may be distributed from the queue to the portions of the destination logic according to the virtual channels identified. Signal data may be unpacked from the packets to update the portions of the destination logic for the destination logic to emulate the source logic with a delay for the period of the trace.
"In yet another aspect of the invention, packets may be generated to represent signal data from a plurality of portions of source logic driven by a plurality of clock domains. Each portion may belong to one of the clock domains. The packets may be formatted according to a packet format including a header field and a payload field. The payload field may carry the signal data. The header field may carry identifiers identifying virtual channels mapping the plurality of portions of the source logic to a plurality of portions of destination logic cloning the source logic. Each packet may be stored in one of a plurality of queues corresponding to the plurality of portions of the source logic. The packets may be arbitrated from the plurality of queues interleaved into a packet stream synchronous with each of the clock domains for distribution to the destination (or target) logic according to the virtual channels.
"In yet another aspect of the present invention, an integrated circuit may comprise a plurality of portions of source logic, operating under a plurality of different clock domains, and a plurality of portions of destination logic replicating the source logic. A storage in the integrated circuit may store virtual channels mapping the plurality of portions of the source logic to the plurality of portions of the destination logic. Concentrator logic in the integrated circuit may serialize packets carrying signal data from the plurality of portions of the source logic into a queue in the storage for a delay. Each packet may identify one of the virtual channels. Distributor logic in the integrated circuit may distribute the signal data from the packets retrieved from the queue to the portions of the destination logic according to the virtual channels subsequent to the delay.
"In yet another aspect of the present invention, a plurality of portions of source logic may be selected from one or more ICs for replication. Packing logic may be inserted to the source logic to generate packets for representing signal data of the selected portions of the ICs. Each packet may include a source identifier identifying one selected portion. Unpacking logic may be inserted to destination logic replicating the selected portions of the source logic. Signal data may be extracted from received packets in the unpacking logic for the replicated portions. Each received packet may include a destination identifier identifying one of the replicated portions. Switching logic may be configured to map the destination identifiers to the source identifiers as virtual channels to forward the signal data from the selected portions to the replicated portions via delay logic recording a trace of the signal data over a delay period. A representation of the ICs may be displayed in display device. A hardware description language (HDL) code may be compiled to generate a technology independent RTL (register transfer level) netlists representing the ICs.
"In yet another aspect of the present invention, a packet switch hub may concentrate data packets carrying signal data of different clock domains from a source circuit into a single packet stream in a single buffer, e.g. a FIFO, utilizing nearly full potential bandwidth of a memory (e.g. off-chip memory). The packets may be put in memory in approximately (within an arbiter error margin) the order they happen in real time for distribution to a destination circuit. The capability of using one single buffer may allow the packet switch hub to eliminate the complexity of synchronizing separate buffers corresponding to different clock domains. In other embodiments, the packet switch hub may provide the flexibility to route signals from chip to chip, capturing characterization data, and/or sourcing test vectors for system bring-up.
"The present invention includes methods and apparatuses which perform these methods, including data processing systems which perform these methods, and computer readable media which when executed on data processing systems cause the systems to perform these methods.
"Other features of the present invention will be apparent from the accompanying drawings and from the detailed description which follows."
For more information, see this patent: Erickson, Robert. Packet Switch Based Logic Replication. U.S. Patent Number 8638792, filed
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