The assignee for this patent, patent number 8637913, is
Reporters obtained the following quote from the background information supplied by the inventors: "Exemplary embodiments of the present invention relate to a nonvolatile memory device and a method for fabricating the same, and more particularly, to a nonvolatile memory device having a three-dimensional structure including a plurality of memory cells that are vertically stacked from a substrate and a method for fabricating the same.
"A nonvolatile memory device is a memory device where stored data is retained even when power is not supplied. An example of nonvolatile memory devices is a flash memory device.
"The degree of integration for a memory device with a two dimensional structure may reach a limit. A three-dimensional structure for a memory device may provide further integration and storage capacity. A three-dimensional structure for a memory device includes a plurality of memory cells stacked along a channel vertically protruding from a silicon substrate and a selection transistor disposed over or under the plurality of memory cells. Since the channel in a three-dimensional memory device structure has a pillar-like shape with a narrow width, wells cannot be formed into various shapes and types as in the memory device with the two-dimensional structure. Therefore, wells are formed by ion-implanting one type of impurities at both ends of the channel. In general, n-type wells are formed by ion-implanting n-type impurities because the mobility of electrons is high.
"In a nonvolatile memory device, a positive voltage may be applied to a channel when performing an erase operation. Since a three-dimensional nonvolatile memory device has the pillar-like channel as described above, a voltage transfer delay time corresponding to a minority carrier generation time may result. To avoid minority carrier generation time in the three-dimensional nonvolatile memory device, an erase operation is performed in such a way to induce GIDL (gate induced drain leakage) using a selection transistor. More specifically, by generating a number of electron-hole pairs that implement GIDL, a positive voltage can be quickly transferred to the channel.
"Thus, in order to increase the operating speed of a device, a memory device may induce a large amount of GIDL. To induce a large amount of GIDL, the density of the impurities ion-implanted into both ends of a channel, in particular, the density of the impurities in a region adjacent to the edge of the gate of the selection transistor, should be increased.
"However, because the channel is generally formed of a polycrystalline semiconductor material, for example, polysilicon, the following features exist when increasing the density of the impurities ion-implanted into both ends of the channel.
"Since the impurities ion-implanted into both ends of the channel may diffuse during a subsequent heat-treatment process, maintaining a desired impurity profile may be difficult. Accordingly, the GIDL may not be induced at a desired level, and, therefore, an erase operation may not be able to increase in speed, which may deteriorate the operation characteristics of the device. In addition, since diffused impurities are placed below the gate of the selection transistor, the threshold voltage of the selection transistor is likely to change, which may degrade the reliability of the device."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "Embodiments of the present invention are directed to a nonvolatile memory device and a method for fabricating the same, which forms a region doped with impurities at a high density to a desired depth in the upper end of a channel and may minimize diffusion of doped impurities.
"In accordance with an embodiment of the present invention, a nonvolatile memory device includes a channel vertically extending from a substrate, wherein the channel comprises a first region that is doped with first impurities and a second region that is disposed under the first region; a plurality of memory cells and a selection transistor stacked over the substrate along the channel; and a diffusion barrier interposed between the first region and the second region, wherein a density of the first impurities is higher than a density of impurities of the second region.
"In accordance with another embodiment of the present invention, a method for fabricating a nonvolatile memory device includes stacking a plurality of memory cells and a selection transistor along a channel that vertically extends from a substrate; forming a trench by removing an upper portion of the channel; forming a diffusion barrier over a bottom of the trench; and forming a semiconductor pattern doped with first impurities over the diffusion barrier in the trench, wherein a density of the first impurities is higher than a density of impurities of the channel."
For more information, see this patent: Yoo, Hyun-Seung; Choi, Eun-Seok. Nonvolatile Memory Device and Method for Fabricating the Same. U.S. Patent Number 8637913, filed
Keywords for this news article include: Electronics,
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