The assignee for this patent, patent number 8637135, is
Reporters obtained the following quote from the background information supplied by the inventors: "Generally, transistor active areas within a given semiconductor substrate surface area all have a uniform length, such that the surface area that comprises the active areas is rectangular with each active area's length being the length of the rectangular area. However, this patterning may result in higher corner stress in each active area and in higher stress in each active area and the shallow trench isolation (STI) adjoining the active area. For example, the oxide in the STI may cause a tensile stress in the STI and a compressive stress in the active area. Further, this patterning generally creates more difficulty in processing, particularly in etching. This may be because occasionally different spaces between adjacent active areas cause different loading effects and chemical reactions such that keeping the active areas uniform may be difficult.
"These problems may become more pronounced as transistor sizes are further scaled down. The problems may be present in both planar field effect transistors and in fin field effect transistors (FinFETs), but may be more problematic in FinFETs. Accordingly, there is a need in the art to overcome these problems and disadvantages."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by embodiments.
"In accordance with an embodiment, a semiconductor device comprises at least three active areas. The at least three active areas are proximate. Longitudinal axes of the at least three active areas are parallel, and each of the at least three active areas comprises an edge intersecting the longitudinal axis of the respective active area. The edges of the at least three active areas form an arc.
"Another embodiment is a method for forming a semiconductor device. The method comprises providing a semiconductor substrate, forming a photoresist layer over the semiconductor substrate, patterning the photoresist layer over the semiconductor substrate to expose an exposed portion of the semiconductor substrate using a photomask, and etching the exposed portion of the semiconductor substrate such that an edge of the exposed portion of the semiconductor substrate defines edges of active areas. The photomask comprises a transparent area comprising a curved edge, and the curved edge defines the edge of the exposed portion of the semiconductor substrate. Each active area comprises a longitudinal length intersecting one respective edge.
"A further embodiment is a method for forming a semiconductor device. The method comprises providing a semiconductor substrate, forming fins on the semiconductor substrate, and patterning the fins such that each of the fins comprises an edge and the edges of the fins form an arc."
For more information, see this patent: Lee, Tsung-Lin; Yu, Shao-Ming. Non-Uniform Semiconductor Device Active Area Pattern Formation. U.S. Patent Number 8637135, filed
Keywords for this news article include: Electronics,
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