The patent's assignee for patent number 8639994 is
News editors obtained the following quote from the background information supplied by the inventors: "Integrated circuits having memory arrays that are designed and manufactured with memory built-in self test (MBIST) circuitry are well-known in the art. An example of an integrated circuit incorporating MBIST circuitry is set forth in U.S. Pat. No. 7,340,658 that is assigned to the assignee of the present invention. That patent also provides background information regarding the utility and advantages provided by MBST circuitry in the design and manufacturer of integrated circuits.
"Integrated circuit employing MBIST generally include multiple different size arrays of memory elements that require testing. Typically, during MBST testing, a test vector is written into an array and then a read operation is performed with the results analyzed to confirm proper operation of the array under the test vector. Within a given component or section of an integrated circuit, each array of that component is conventionally tested in series in order to analyze any result of the application of the respective test vector with the respective array."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features.
"In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. The parallel initialization serves, inter alia, to reduce the time required to set the memory elements within the arrays to a desired state. Accordingly, this feature assists the integrated circuit to expeditiously exit a power off state with respect to the components in which it is implemented.
"In a preferred embodiment, the MBIST circuitry includes an MBIST master circuit configured to control multiple MBIST slave circuits where the MBIST slave circuits are each associated with a set of arrays within a respective integrated circuit component. In such embodiment, it is preferred that the master MBST circuitry is configured to issue a global built-in self initialization (BISI) instruction directing the multiple MBIST slave circuits to input initialization vectors in parallel into their respective associated arrays in order to quickly set the memory components of the arrays into a desired state for integrated circuit operation. Preferably, the MBIST master circuit is similarly configured to provide global instructions to the MBIST slave circuitry to input in parallel desired stress vectors and inverse stress vectors to result in a pre-stressed integrated circuit.
"In another aspect of the invention, the MBST circuitry is configured to input stress and inverse stress vectors into the arrays of the integrated circuit component to set the memory elements of the arrays to a first state and then to an inverse state. Preferably, the stress and inverse stress vectors are applied during a burn-in operation to maintain each of the two opposing states for a desired time during burn-in in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond a desired infancy stage of the integrated circuit. Preferably, the time allocated for the memory elements to be maintained in the first state during a burn-in operation is roughly equal to the time the memory elements are to be maintained in the inverse state during the burn-in operation. To the extent that the application of the stress and inverse stress vectors by the MBIST circuitry during a burn-in does not cause a failure of the integrated circuit component, a pre-stressed component having greater reliability is produced.
"The stress and inverse stress vectors may be applied alternately or in series. Preferably, each vector is applied the same number of times to maintain the respective memory states for substantially the same amount of time. In a preferred embodiment, the either the stress or inverse stress vectors that are used are the same as the initialization vectors used for setting the memory elements of the arrays to a desired state for integrated circuit operation. In a preferred embodiment, the stress vectors are applied in parallel to the arrays of the component of the integrated circuits. Thereafter the inverse stress vectors are applied in parallel to the arrays.
"Other objects and advantages of the present invention will become apparent from the drawings and following detailed description of presently preferred embodiments."
For additional information on this patent, see: Chen, Wei-Yu; Badgett, Kevin;
Keywords for this news article include:
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