News Column

Patent Issued for Flexible SoC Design Verification Environment

February 13, 2014

By a News Reporter-Staff News Editor at Computer Weekly News -- Apple Inc. (Cupertino, CA) has been issued patent number 8639981, according to news reporting originating out of Alexandria, Virginia, by VerticalNews editors.

The patent's inventor is Chong, Andrew K. (Cupertino, CA).

This patent was filed on August 29, 2011 and was published online on January 28, 2014.

From the background information supplied by the inventors, news correspondents obtained the following quote: "The present invention relates generally to design verification tools, and in particular to design verification systems and methods for developing systems on chips.

"The complexity of systems on chips (SoCs) continues to grow as increasing numbers of transistors are incorporated into SoCs. SoC implementations can include one or more processors and a variety of peripherals, all integrated onto one semiconductor substrate. The peripherals can be in various states of operation at the same time that the processor(s) are performing numerous other operations. The number of possible states in the SoC, all of which must generally provide correct operation, increases exponentially with complexity. Such complexity must be tested during the design and manufacture of the SoC to provide reasonable assurance that the SoC will function as designed and that the design is correct.

"One common methodology used for the testing and debugging of SoCs is based on the Institute of Electrical and Electronics Engineers (IEEE) 1149.1 standard test access port and boundary-scan architecture, also known as joint test action group (JTAG). Debug controllers often utilize signals that are compliant with the JTAG protocol for testing actual physical SoCs. Prior to fabricating an actual SoC, most SoCs are modeled and simulated in a variety of simulation platforms. For example, various emulators have been developed that offer the ability to simulate SoC designs prior to fabricating the SoC in silicon. However, some of these emulators do not include a JTAG interface. Furthermore, debug controllers which execute commands and scripts for testing an actual physical SoC, typically use a JTAG interface to interface to the SoC when the SoC is fabricated. However, these debug controllers are not able to use this JTAG interface to communicate with emulators that lack a JTAG interface.

"As the size of SoCs continues to increase, the amount of testing and debugging that needs to be performed also increases. Some tests may be lengthy and involve many lines of code. In addition, software developers are often required to use a low-level JTAG protocol compliant language to write debug and testing commands that will be incorporated into various testing scripts. Furthermore, the scripts that are used to test a hardware model of a SoC typically cannot be reused when a development board with a fabricated SoC is being tested. This means that the software developer will be required to write new scripts to test the physical SoC, instead of being able to reuse the existing scripts that were used to test the model of the SoC."

Supplementing the background information on this patent, VerticalNews reporters also obtained the inventor's summary information for this patent: "In one embodiment, a design verification system may include a plurality of elements such as a host computer, debugger, and emulator. The emulator may include one or more software models of SoCs. In another embodiment, the design verification system may include a SoC on a development board in place of the emulator. One or more scripts may be invoked on the host computer, and the script(s) may include one or more commands in a first language. The first language may be a high-level language that obscures the details of a lower-level language used to control the DUT. In one embodiment, the first language may be JTAG state microcode (JSM).

"The host computer may source a translator application to the debugger. The debugger may utilize the translator application to convert the script(s) from a first language into commands of a second language. In one embodiment, the second language may be a JTAG protocol compliant language. The debugger may convey the commands in the second language to the SoC model in the emulator. In another embodiment, the debugger may convey the commands in the second language to the SoC on the development board. The commands in the second language may be executed within the DUT to generate control signals and perform one or more tests. The same scripts that are used to perform debug and verification operations on the SoC model in the emulator may be reused to perform operations on the SoC on the development board.

"These and other features and advantages will become apparent to those of ordinary skill in the art in view of the following detailed descriptions of the approaches presented herein."

For the URL and additional information on this patent, see: Chong, Andrew K.. Flexible SoC Design Verification Environment. U.S. Patent Number 8639981, filed August 29, 2011, and published online on January 28, 2014. Patent URL:

Keywords for this news article include: Software, Apple Inc..

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC

For more stories covering the world of technology, please see HispanicBusiness' Tech Channel

Source: Computer Weekly News

Story Tools