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Patent Application Titled "Memory Element and Programmable Logic Device" Published Online

February 12, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- According to news reporting originating from Washington, D.C., by VerticalNews journalists, a patent application by the inventor Ikeda, Takayuki (Atsugi, JP), filed on July 12, 2013, was made available online on January 30, 2014.

No assignee for this patent application has been made.

Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates to a memory element. In particular, the present invention relates to a memory element where data is stored in a node which is brought into a floating state by turning off a transistor a channel of which is formed in an oxide semiconductor layer. The present invention relates to a semiconductor device (e.g., a programmable logic device) including the memory element.

"Transistors using an oxide semiconductor as a material of an active layer have been developed. For example, Patent Document 1 discloses a memory element where data can be stored in a node which is brought into a floating state by turning off the transistor. Note that the memory element has a nonvolatile property (see paragraph 0044 in Patent Document 1)."

In addition to obtaining background information on this patent application, VerticalNews editors also obtained the inventor's summary information for this patent application: "For driving electronic devices, a plurality of power source potentials with different levels are needed. For example, to drive a digital circuit, a high power source potential corresponding to data '1' and a low power source potential corresponding to data '0' are needed at least. Note that the number of power source potentials needed for driving an electronic device is preferably small, which can simplify the structure of the electronic device.

"The memory element disclosed in Patent Document 1 is preferably driven using only a high power source potential corresponding to data '1' and a low power source potential corresponding to data '0'. Note that in the memory element disclosed in Patent Document 1, data is written to a predetermined node through a source and a drain of an n-channel transistor. In this case, a potential equal to the high power source potential corresponding to data '1' cannot be written to the node.

"Specifically, in the case where the high power source potential corresponding to data '1' is written to the node, the transistor is turned on while the high power source potential is supplied to a gate and the drain of the transistor. In addition, the transistor is turned off when the potential of the source of the transistor is increased to a potential which is obtained by subtracting the threshold voltage of the transistor from the high power source potential. Note that the node is electrically connected to the source of the transistor. Accordingly, the potential of the node is not increased to exceed a potential which is obtained by subtracting the threshold voltage of the transistor from the high power source potential.

"Here, in the case where the potential of the node is lower than the high power source potential corresponding to data '1', detection of the data might be delayed or become difficult. In view of the problem, an object of one embodiment of the present invention is to provide a memory element where a desired potential can be stored as data without an increase in the number of power source potentials.

"One embodiment of the present invention is a memory element where data is stored in a node which is brought into a floating state by turning off a transistor. In addition, one embodiment of the present invention is a memory element where the potential of a gate of the transistor can be increased by capacitive coupling between the gate and a source of the transistor.

"For example, one embodiment of the present invention is a memory element that store data in a node which is brought into a floating state by turning off a first n-channel transistor. The memory element includes a first wiring configured to supply a high power source potential and a low power source potential, a second wiring configured to supply the high power source potential, and a second n-channel transistor, a gate of which is electrically connected to the second wiring, one of a source and a drain of which is electrically connected to the first wiring, and the other of the source and the drain of which is electrically connected to a gate of the first n-channel transistor.

"In the memory element of one embodiment of the present invention, the potential of a gate of the first transistor can be increased by increasing the potential of the first wiring to the high power source potential corresponding to data '1'. Specifically, the potential of the gate of the first transistor can be increased to a potential which is obtained by subtracting the threshold voltage of the second transistor from the high power source potential. In this case, the first transistor is turned on. Then, in the memory element, the potential of a drain of the first transistor can be increased to the high power source potential. In this case, the potential of the gate of the first transistor is further increased by capacitive coupling between the gate and a source of the first transistor. Therefore, the potential of the source of the first transistor can be increased to the high power source potential. That is, in the memory element, the potential of a node where data is stored can be increased to the high power source potential. As a result, in the memory element, detection of data can be performed more quickly and more easily.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1A illustrates a structural example of a memory element and FIGS. 1B to 1F show an example of a method for driving a memory element.

"FIGS. 2A to 2D illustrate specific examples of a memory element.

"FIG. 3 illustrates a specific example of a memory element.

"FIG. 4A illustrates a structural example of a memory element and FIGS. 4B to 4F show an example of a method for driving a memory element.

"FIG. 5 illustrates a structural example of a memory device.

"FIG. 6A illustrates a structural example of a programmable logic device and FIG. 6B illustrates a structural example of a switch matrix.

"FIG. 7A illustrates a structural example of a wiring selection circuit and FIG. 7B illustrates a structural example of a programmable switch.

"FIG. 8 illustrates a structural example of a programmable switch.

"FIG. 9 illustrates a structural example of a transistor.

"FIG. 10 illustrates a structural example of a memory element.

"FIGS. 11A to 11F illustrate e specific examples of electronic devices."

For more information, see this patent application: Ikeda, Takayuki. Memory Element and Programmable Logic Device. Filed July 12, 2013 and posted January 30, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4803&p=97&f=G&l=50&d=PG01&S1=20140123.PD.&OS=PD/20140123&RS=PD/20140123

Keywords for this news article include: Patents, Electronics, Semiconductor, Capacitive Coupling, Programmable Logic Device.

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Source: Electronics Newsweekly


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