News Column

"Method of Forming Semiconductor Structure" in Patent Application Approval Process

February 12, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent application by the inventors Hsu, Chen-Chiu (Hsinchu City, TW); Lai, Tung-Ming (Hsinchu City, TW); Hsueh, Kai-An (Miaoli County, TW); Huang, Ming-De (New Taipei City, TW), filed on October 1, 2012, was made available online on January 30, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application has not been assigned to a company or institution.

The following quote was obtained by the news editors from the background information supplied by the inventors: "The invention relates to a method of forming a semiconductor structure, and more particularly, to a method of forming a semiconductor structure in which a memory unit is integrated with a peripheral logic device, a resistor, or a capacitor.

"Data may be repeatedly written into, read from, and erased from non-volatile memory devices, and the data stored in the non-volatile memory devices may be retained even after power supplies of the devices are cut off. Therefore, the non-volatile memory devices have been extensively applied to personal computers and electronic equipment.

"An erasable programmable read-only memory with tunnel oxide (i.e., EPROM with tunnel oxide, ETOX) is one of the common memory cell structures. In the ETOX, a floating gate and a control gate for performing erasing/writing operations are made of doped polysilicon. During the ETOX operation, in order to prevent the problem of data error due to over-erasing/writing phenomenon, a select transistor is serially connected at one side of the memory cell to form a two-transistor (2T) structure. When multiple-time programming (MTP) is performed, the programming and reading operations of the memory cell can be controlled by the select transistor.

"With the development of a multi-functional chip, a memory unit in a cell area as well as a logic device, a resistor, or a capacitor in a periphery area may be formed on the same chip. However, the process of manufacturing the memory unit is often separated from the process of manufacturing the peripheral device; hence, several photo masks may be required, and the manufacturing processes are rather complicated. This may increase the manufacturing costs and weaken the competitiveness."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "The invention is directed to a method of forming a semiconductor structure. According to the method, a memory unit may be easily integrated with a peripheral logic device, a resistor, or a capacitor through an existing manufacturing process.

"In an embodiment of the invention, a method of forming a semiconductor structure is provided. A substrate having a cell area and a logic circuit area is provided. An oxide material layer and a first conductive material layer are sequentially formed on the substrate in the cell area and in the logic circuit area. A patterning step is performed to form a first stacked structure on the substrate in the cell area and form a second stacked structure on the substrate in the logic circuit area. A first spacer is formed on a sidewall of the first stacked structure, and a second spacer is formed on a sidewall of the second stacked structure. At least two first doped regions are formed in the substrate beside the first stacked structure, and two second doped regions are formed in the substrate beside the second stacked structure. A dielectric layer and a second conductive layer are formed at least on the first stacked structure. The first stacked structure, the dielectric layer, and the second conductive layer in the cell area constitute a charge storage structure, and the second stacked structure is a logic transistor.

"According to an embodiment of the invention, a select transistor is simultaneously formed at one side of the first stacked structure on the substrate in the cell area in the patterning step. A third spacer is simultaneously formed on a sidewall of the select transistor in the step of forming the first and second spacers. The first doped regions are further formed in the substrate beside the select transistor, and the charge storage structure and the select transistor share one of the first doped regions.

"According to an embodiment of the invention, the dielectric layer has a single-layer structure or a multi-layer structure.

"According to an embodiment of the invention, the dielectric layer and the second conductive layer further extend, along the sidewall of the first stacked structure, to the substrate at one side of the first stacked structure in the cell area, and the first doped regions are respectively disposed in the substrate beside the second conductive layer.

"According to an embodiment of the invention, the dielectric layer has a single-layer structure.

"According to an embodiment of the invention, the substrate further has a resistor area.

"According to an embodiment of the invention, a third stacked structure is simultaneously formed on the substrate in the resistor area in the patterning step. A third spacer is simultaneously formed on a sidewall of the third stacked structure in the step of forming the first and second spacers. The dielectric layer and the second conductive layer are further formed on the third stacked structure and expose a portion of an upper surface of the third stacked structure.

"According to an embodiment of the invention, the method of forming the semiconductor structure further includes: forming a fourth spacer on a sidewall of the charge storage structure, forming a fifth spacer on the sidewall of the second stacked structure, forming a sixth spacer on sidewalls of the dielectric layer and the second conductive layer on the third stacked structure, and forming a silicide layer at least on an upper surface of the charge storage structure, on an upper surface of the second stacked structure, on the portion of the upper surface of the third stacked structure, and on an upper surface of the second conductive layer on the third stacked structure.

"According to an embodiment of the invention, a material of the silicide layer includes cobalt silicide.

"According to an embodiment of the invention, the method of forming the semiconductor structure further includes forming two conductive plugs that are electrically connected to the silicide layer on the third stacked structure.

"According to an embodiment of the invention, the dielectric layer and the second conductive layer are further formed on the substrate in the resistor area to constitute a third stacked structure.

"According to an embodiment of the invention, the method of forming the semiconductor structure further includes: forming a third spacer on a sidewall of the charge storage structure, forming a fourth spacer on the sidewall of the second stacked structure, forming a fifth spacer on a sidewall of the third stacked structure, and forming a silicide layer at least on an upper surface of the charge storage structure, on an upper surface of the second stacked structure, and on an upper surface of the third stacked structure.

"According to an embodiment of the invention, a material of the silicide layer includes cobalt silicide.

"According to an embodiment of the invention, the silicide layer is further formed on the substrate beside the third stacked structure.

"According to an embodiment of the invention, the method of forming the semiconductor structure further includes forming two conductive plugs that are electrically connected to the silicide layer located on the substrate beside the third stacked structure.

"According to an embodiment of the invention, the substrate further has a capacitor area.

"According to an embodiment of the invention, a third stacked structure is simultaneously formed on the substrate in the capacitor area in the patterning step. A third spacer is simultaneously formed on a sidewall of the third stacked structure in the step of forming the first and second spacers. The dielectric layer and the second conductive layer are further formed on the third stacked structure, and a sidewall of the dielectric layer and a sidewall of the second conductive layer are aligned to the sidewall of the third stacked structure. The third stacked structure, the dielectric layer, and the second conductive layer in the capacitor area constitute a capacitor.

"According to an embodiment of the invention, the method of forming the semiconductor structure further includes forming a fourth spacer on a sidewall of the charge storage structure, forming a fifth spacer on the sidewall of the second stacked structure, and forming a sixth spacer on a sidewall of the capacitor.

"According to an embodiment of the invention, two third doped regions are simultaneously formed in the substrate beside the capacitor in the step of forming the first doped regions and the second doped regions.

"In view of the above, the method of forming the semiconductor structure described herein may be integrated into the existing manufacturing process (e.g., a logic manufacturing process or a CMOS manufacturing process). Thereby, a memory unit may be easily integrated with a peripheral logic device, a resistor, or a capacitor through the existing manufacturing process, which significantly reduces the manufacturing costs and enhances competitiveness. Here, the memory unit may have an ETOX structure or a two-transistor (2T) structure including a charge storage structure and a select transistor, and a one-time programming (OTP) operation or a multi-time programming (MTP) operation may be performed based on actual requirements.

"Several exemplary embodiments accompanied with figures are described in detail below to further explain the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

"The accompanying drawings are included to provide further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments and, together with the description, serve to explain the principles of the invention.

"FIG. 1A through FIG. 1E are schematic cross-sectional views illustrating a method of forming a semiconductor structure according to a first embodiment of the invention.

"FIG. 2A through FIG. 2E are schematic cross-sectional views illustrating a method of forming a semiconductor structure according to a second embodiment of the invention.

"FIG. 3A through FIG. 3C are schematic cross-sectional views illustrating a method of forming a semiconductor structure according to a third embodiment of the invention.

"FIG. 4A through FIG. 4F are schematic cross-sectional views illustrating a method of forming a semiconductor structure according to a fourth embodiment of the invention.

"FIG. 5A through FIG. 5F are schematic cross-sectional views illustrating a method of forming a semiconductor structure according to a fifth embodiment of the invention.

"FIG. 6A through FIG. 6E are schematic cross-sectional views illustrating a method of forming a semiconductor structure according to a sixth embodiment of the invention.

"FIG. 7 is a schematic cross-sectional view illustrating another semiconductor device according to the sixth embodiment of the invention."

URL and more information on this patent application, see: Hsu, Chen-Chiu; Lai, Tung-Ming; Hsueh, Kai-An; Huang, Ming-De. Method of Forming Semiconductor Structure. Filed October 1, 2012 and posted January 30, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=2095&p=42&f=G&l=50&d=PG01&S1=20140123.PD.&OS=PD/20140123&RS=PD/20140123

Keywords for this news article include: Patents, Electronics, Semiconductor.

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Source: Electronics Newsweekly


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