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"High Throughput Epitaxial Lift off for Flexible Electronics" in Patent Application Approval Process

February 12, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent application by the inventors Cheng, Cheng-Wei (White Plains, NY); Shiu, Kuen-Ting (White Plains, NY), filed on September 23, 2013, was made available online on January 30, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to International Business Machines Corporation.

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present disclosure relates to semiconductor device manufacturing, and more particularly to a method of removing a semiconductor device layer from an underlying base substrate.

"Devices that can be produced in thin-film form have three clear advantages over their bulk counterparts. First, by virtue of less material used, thin-film devices ameliorate the materials cost associated with device production. Second, low device weight is a definite advantage that motivates industrial-level effort for a wide range of thin-film applications. Third, if dimensions are small enough, devices can exhibit mechanical flexibility in their thin-film form. Furthermore, if a device layer is removed from a substrate that can be re-used, additional fabrication cost reduction can be achieved.

"Efforts to (i) create thin-film substrates from bulk materials (i.e., semiconductors) and (ii) form thin-film device layers by removing device layers from an the underlying bulk substrates on which they were formed are ongoing."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "A method of removing a semiconductor device layer from an underlying base substrate is provided in which a sacrificial phosphide-containing layer is formed between a semiconductor device layer and a base substrate. In some embodiments, a semiconductor buffer layer can be formed on an upper surface of the base substrate prior to forming the sacrificial phosphide-containing layer. The resultant structure is then etched utilizing a non-HF etchant to release the semiconductor device layer from the base substrate. After releasing the semiconductor device layer from the base substrate, the base substrate can be re-used.

"The ELO process of the present disclosure has a lower cost associated therewith. Moreover, and as mentioned above, the base substrate can be re-used after performing the ELO process of the present disclosure.

"In one embodiment, the method of the present disclosure includes forming a sacrificial phosphide-containing layer on an upper surface of a base substrate. Next, a semiconductor device layer is formed on an upper surface of the sacrificial phosphide-containing layer. The sacrificial phosphide-containing layer is then removed from between the semiconductor device layer and the base substrate by etching with a non-HF containing etchant.

"In another embodiment, the method of the present disclosure includes forming a semiconductor buffer layer on an upper surface of a base substrate. A sacrificial phosphide-containing layer is then formed on an upper surface of the semiconductor buffer layer. Next, a semiconductor device layer is formed on an upper surface of the sacrificial phosphide-containing layer. The sacrificial phosphide-containing layer located between the semiconductor device layer and the base substrate is then removed by etching with a non-HF containing etchant. Next, the semiconductor buffer layer can be removed from atop the base substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a pictorial representation (through a cross sectional view) depicting an initial structure including a base substrate that can be employed in accordance with one embodiment of the present disclosure.

"FIG. 2 is a pictorial representation (through a cross sectional view) depicting the structure of FIG. 1 after forming an optional semiconductor buffer layer on an upper surface of the base substrate.

"FIGS. 3A and 3B are pictorial representations (through cross sectional views) depicting the structures of FIG. 1 and FIG. 2, respectively, after forming a sacrificial phosphide-containing layer thereon.

"FIGS. 4A and 4B are pictorial representations (through cross sectional views) depicting the structures of FIGS. 3A and 3B, respectively, after forming a semiconductor device layer thereon.

"FIGS. 5A and 5B are pictorial representations (through cross sectional views) depicting the structures of FIGS. 4A and 4B, respectively, during an initial stage of an etching process in accordance with the present disclosure.

"FIGS. 6A and 6B are pictorial representations (through cross sectional views) depicting the structures of FIGS. 5A and 5B, respectively, after performing the etching process in accordance with the present disclosure.

"FIG. 7 is a pictorial representation (through a cross sectional view) depicting the structure of FIG. 6B after removing the optional semiconductor buffer layer from the upper surface of the base substrate.

"FIG. 8 is a pictorial representation (through a cross sectional view) depicting a structure that includes a first protection layer located between a semiconductor device layer and a sacrificial phosphide-containing layer that can be employed in one embodiment of the present disclosure.

"FIG. 9 is a pictorial representation (through a cross sectional view) depicting the structure of FIG. 8 after patterning the semiconductor device layer and forming a second protection layer thereon.

"FIG. 10 is a pictorial representation (through a cross sectional view) depicting the structure of FIG. 9 during an initial stage of an etching process in accordance with the present disclosure."

URL and more information on this patent application, see: Cheng, Cheng-Wei; Shiu, Kuen-Ting. High Throughput Epitaxial Lift off for Flexible Electronics. Filed September 23, 2013 and posted January 30, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=2056&p=42&f=G&l=50&d=PG01&S1=20140123.PD.&OS=PD/20140123&RS=PD/20140123

Keywords for this news article include: Electronics, Semiconductor, International Business Machines Corporation.

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Source: Electronics Newsweekly


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