News Column

"Delay Locked Loop Circuit and Method of Driving the Same" in Patent Application Approval Process

February 12, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent application by the inventor NA, Kwang-Jin (Gyeonggi-do, KR), filed on November 27, 2012, was made available online on January 30, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application is assigned to Sk Hynix Inc.

The following quote was obtained by the news editors from the background information supplied by the inventors: "Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a Delay-Locked Loop (DLL) circuit for a semiconductor device and a method of driving the same.

"In general, a DLL circuit is used to provide a delay locked clock having a phase, which is earlier than the phase of an internal clock by a specific time, obtained by converting an external clock. An internal clock used in a semiconductor integrated circuit is delayed through a clock buffer and transmission lines, and thus, a phase difference occurs between the internal clock and an external clock. A DLL circuit may be used to solve concerns in which the output timing of output data is not synchronized due to the phase difference.

"FIG. 1 is a waveform diagram illustrating the operation of a conventional DLL circuit.

"As shown in FIG. 1, the DLL circuit outputs a delay locked clock signal DLL_OUT having a timing that is earlier than a timing of a received internal clock INT_CLK by a specific time. A semiconductor memory device synchronizes data D0, D1, and D2 with the delay locked clock signal DLL_OUT and outputs the synchronized data. When the semiconductor memory device outputs the data as described above, the data seems to be precisely outputted in response to an external signal EXT_CLK.

"When the DLL circuit completes the delay locked operation, a locking detector detects this completion and activates a locking detection signal. When the locking detector activates the locking detection signal, the semiconductor memory device externally outputs data synchronized with a transition of a delay locked clock that is outputted from the DLL circuit.

"If the locking detector determines that a delay locked operation has been completed even when the delay locked operation has not been completed, and thus, activates a locking detection signal, the semiconductor memory device erroneously detects that the delay locked operation has been completed and outputs data externally. In this case, the output data may not be synchronized with an external system clock.

"Furthermore, a delay locked operation may not be completed because a locking detection signal is not activated when the delay locked operation is completed. Even in this case, the output data may not be synchronized with an external system dock. As a result, an external device may not properly receive data outputted from a semiconductor memory device,"

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventor's summary information for this patent application: "Exemplary embodiments of the present invention are directed to providing a DLL capable of detecting delay locking in an initial delay locking operation without an error.

"Other exemplary embodiments of the present invention are directed to providing a DLL that may prevent a half phase locking failure in which a coarse delay lock signal is generated in a half phase due to the introduction of power noise in the initial locking process of the DLL used in a semiconductor device and prevent a phase locking miss in which delay locking is missed in a phase-locked position.

"In accordance with an embodiment of the present invention, a DLL includes a coarse delay line configured to have a plurality of unit delay and delay an reference clock to output a delayed clock; a fine delay line configured to delay the delayed clock to output a delayed output clock; a replica delay unit configured to delay the delayed output clock by an expected modeling value to output a feedback clock; a phase detection unit configured to compare a phase of the feedback clock with a phase of the reference clock to generate a first phase detection signal based on a result of the comparison, compare the phase of the reference clock with a phase of the feedback clock delayed by the unit delay to generate a second phase detection signal based on a result of the comparison, and compare the phase of the reference clock with a phase of the feedback clock advanced by the unit delay to generate a third phase detection signal based on a result of the comparison; a locking detection unit configured to output a locking signal by selecting a first locking detection signal generated by comparing a previous state and a current state of the second phase detection signal with each other or a second locking detection signal generated in response to logic levels of the first to third phase detection signals at the same timing; and a control unit configured to control the coarse delay line and the fine delay line in response to the locking signal and the first phase detection signal.

"In accordance with another embodiment of the present invention, a DLL includes a variable delay unit configured to comprise a plurality of unit delays to delay a reference clock; a replica delay unit configured to delay an output clock of the variable delay unit by an expected modeling value to output a feedback clock; a first phase detection unit configured to compare a phase of the reference clock with a phase of the feedback clock to generate a first phase detection signal based on a result of the comparison; a second phase detection unit configured to compare the phase of the reference clock with a phase of the feedback clock delayed by a unit delay of the variable delay unit to generate a second phase detection signal according to a result of the comparison; a third phase detection unit configured to compare a phase of the reference clock delayed by the unit delay with the phase of the feedback clock to generate a third phase detection signal based on a result of the comparison; a first locking detection unit configured to generate a first locking detection signal by detecting a transition of the second phase detection signal; a second locking detection unit configured to generate a second locking detection signal in response to logic levels of the second and the third phase detection signals corresponding to a logic level of the first phase detection signal; a selection unit configured to output the first locking detection signal or the second locking detection signal as a final locking signal in response to a selection signal generated when the first to third phase detection signals satisfy a specific condition; and a delay control unit configured to control an amount of delay of the variable delay unit in response to the final locking signal and the first phase detection signal.

"In accordance with yet another embodiment of the present invention, a method of driving a DLL includes delaying an reference clock by a coarse delay amount; delaying the delayed reference clock by a fine delay amount to output an output clock; delaying the output clock by an expected modeling value and outputting a feedback clock; comparing a phase of the reference clock with a phase of the feedback clock to generate a first phase detection signal based on a result of the comparison comparing the phase of the reference dock with a phase of the feedback dock delayed by a unit delay amount of the coarse delaying to generate a second phase detection signal based on a result of the comparison, and comparing the phase of the reference clock with a phase of the feedback clock advanced by the unit delay amount of the coarse delaying to generate a third phase detection signal based on a result of the comparison; generating a first locking detection signal by detecting a transition of the second phase detection signal, and generating a second locking detection in response to logic levels of the second and the third phase detection signals; selecting one of the first locking detection signal and the second locking detection signal in response to a selection signal to output a locking signal; and controlling delay amounts of the coarse and fine delays in response to the locking signal and the first phase detection signal.

BRIEF DESCRIPTION OF THE DRAWINGS

"FIG. 1 is a waveform diagram illustrating an operation of a conventional DLL circuit.

"FIG. 2 is a block diagram of a DLL circuit.

"FIG. 3 is a block diagram of a phase detection unit shown in FIG. 2.

"FIG. 4 is a detailed circuit diagram of a coarse locking detection unit shown in FIG. 2 and connected to the phase detection unit of FIG. 3.

"FIG. 5 is a waveform diagram illustrating an operation of the DLL circuit shown in FIGS. 2 to 4.

"FIG. 6 is a waveform diagram illustrating concerns in the operation of the DLL circuit shown in FIGS. 2 to 4.

"FIG. 7 is another block diagram of the phase detection unit shown in FIG. 2.

"FIG. 8 is another block diagram of the coarse locking detection unit shown in FIG. 2 and connected to the phase detection unit of FIG. 7.

"FIG. 9 is a waveform diagram illustrating an operation of the DLL circuit shown in FIGS. 2, 7, and 8.

"FIG. 10 is a waveform diagram illustrating concerns in the operation of the DLL circuit shown in FIGS. 2, 7, and 8.

"FIG. 11 is a block diagram of a coarse locking detection unit in accordance with an embodiment of the present invention.

"FIG. 12 is a detailed circuit diagram of a first locking detector shown in FIG. 11.

"FIG. 13 is a detailed circuit diagram of a second locking detector shown in FIG. 11.

"FIG. 14 is a detailed circuit diagram of a locking selection signal generator shown in FIG. 11.

"FIG. 15 is a flowchart illustrating a method of driving the DLL circuit in accordance with an embodiment of the present invention."

URL and more information on this patent application, see: NA, Kwang-Jin. Delay Locked Loop Circuit and Method of Driving the Same. Filed November 27, 2012 and posted January 30, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4287&p=86&f=G&l=50&d=PG01&S1=20140123.PD.&OS=PD/20140123&RS=PD/20140123

Keywords for this news article include: Electronics, Sk Hynix Inc, Semiconductor.

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Source: Electronics Newsweekly


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