This patent application has not been assigned to a company or institution.
The following quote was obtained by the news editors from the background information supplied by the inventors: "The present invention relates to a data storage device with a FLASH memory and an operating method thereof.
"Today, FLASH memory (e.g.,
"FIG. 1A depicts the storage space of a FLASH memory. The FLASH memory 100 may comprise a plurality of physical blocks BLK1, BLK2, and so forth. Each physical block includes a plurality of physical pages. For example, the physical block BLK1 includes physical pages Page1, Page2, and so forth.
"According to operating characteristics of a FLASH memory, an erase operation is required to release the space of the FLASH memory. An erase operation has to be performed on an entire block. FIG. 1B depicts the data update for a particular logical address. In the physical block BLK, the old data in space Data_Old becomes invalid when the update data is stored in a spare space Data_New. Because the reuse of the space Data_Old requires an erase operation to be performed on the entire physical block BLK, a valid data collection operation (as known as garbage collection) has to be performed on the physical block BLK prior to the erase operation. After collecting all valid data within the physical block BLK (e.g. data in Data_New) to other physical blocks, the physical block BLK is erasable to be released as a free block.
"There are several modes to allocate the storage space of the FLASH memory 100. Typically, the FLASH memory 100 may be allocated according to a block mapping mode or a page mapping mode. FIG. 1C shows that according to a block mapping mode, a physical block (as that defined in FIG. 1A) is allocated to map to a series of consecutive logical addresses at the host for data storage. The series of consecutive logical addresses may form a logical block, which is numbed by 'LBN,' a logical block number. In the block mapping mode, the data indicated by the series of consecutive logical addresses is written into the physical block page by page in the order of the logical addresses (i.e. sequential in the logical address). Thus, when looking up for a physical space corresponding to a logical address, a block mapping table may be referred to first to find the physical block corresponding to the logical block number (LBN) of the logical address, and then the physical page for the logical address is found from the physical block according to a page offset of the logical address. Note that according to the block mapping mode, data is written into a physical block in sequential according to logical addresses. The valid data collection operation, therefore, is frequently performed and results in a considerable burden on the operation efficiency of the FLASH memory. As for the page mapping mode, the sequential write based on the logical addresses is not necessary and each physical block does not particularly correspond to a series of consecutive logical addresses. However, an enormous page mapping table is required to look up to find the physical page for each logical address, wherein the mapping relation of each logical address to each corresponding physical address needs storing in the page mapping table. The resource consumption is still considerable due to huge storage space for the large-sized mapping table as well as the wide search over the mapping table. How to improve the operation efficiency of a FLASH memory without the aforementioned defects of the block mapping and the page mapping modes is an important issue in the field."
In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "A data storage device with a FLASH memory and an operating method of the data storage device is disclosed.
"A data storage device in accordance with an exemplary embodiment of the invention comprises a FLASH memory and a controller. The FLASH memory comprises a plurality of groups of data blocks, a plurality of shared cache blocks (SCBs) and a plurality of dedicated cache blocks (DCBs). Each shared cache block corresponds to a group of data blocks and is shared by the data blocks of the group. Each dedicated cache block corresponds to one hot logical block. The controller is coupled to the FLASH memory. When a logical address of write data is determined to be belonging to a hot logical block, the controller caches the write data into the dedicated cache block corresponding to the hot logical block. When any data block is filled up, the write data requested to be written into the data block is cached into the shared cache block shared by the group of data blocks having the filled-up data block.
"In another exemplary embodiment, an operating method for a data storage device is disclosed, which comprises the following steps: allocating a plurality of groups of data blocks, a plurality of shared cache blocks (SCBs) and a plurality of dedicated cache blocks (DCBs) in a FLASH memory of the data storage device, wherein each shared cache block is shared by the data blocks of the same group, and each dedicated cache block corresponds to a hot logical block; when a logical address of write data is determined to be belonging to a hot logical block, the write data is cached into the dedicated cache block corresponding to the hot logical block, and when the logical address is not belonging to a hot logical block and data block corresponding to the logical address is filled up, the write data is cached into the shared cache block shared by the group of data blocks having the filled-up data block.
"A detailed description is given in the following embodiments with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
"The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
"FIG. 1A shows a storage space provided by a FLASH memory;
"FIG. 1B shows the data update of a particular logical address;
"FIG. 1C shows that, according to a block mapping mode, a physical block is allocated to map to a series of consecutive logical addresses of the host for data storage;
"FIG. 2 depicts a data storage device 200 in accordance with an exemplary embodiment of the invention;
"FIG. 3A shows a data-block mapping table DMT;
"FIG. 3B shows a mapping table SCB_MT;
"FIG. 3C shows a mapping table DCB_MT;
"FIG. 4 is a flowchart depicting operations in response to a write command;
"FIG. 5 is a flowchart depicting operations in response to a read command;
"FIG. 6A depicts an exemplary embodiment of the invention, wherein a valid data collection operation and a block space release operation are performed when writing data to the last physical page of the shared cache block SCB; and
"FIG. 6B depicts an exemplary embodiment of the invention, wherein a valid data collection operation and a block space release operation are performed when writing data to the last physical page of the dedicated cache block DCB."
URL and more information on this patent application, see: ZHANG, Bo; XIU, Chen. Data Storage Device and Operating Method Thereof. Filed
Keywords for this news article include: Patents, Information Technology, Information and
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