News Column

"Collecting Processor Usage Statistics" in Patent Application Approval Process

February 13, 2014



By a News Reporter-Staff News Editor at Computer Weekly News -- A patent application by the inventors Ghemawat, Sanjay (Mountain View, CA); Fikes, Andrew (Los Altos, CA); Taylor, Chris Jorgen (Palo Alto, CA), filed on June 4, 2013, was made available online on January 30, 2014, according to news reporting originating from Washington, D.C., by VerticalNews correspondents.

This patent application has not been assigned to a company or institution.

The following quote was obtained by the news editors from the background information supplied by the inventors: "A computer system typically includes one or more processors. The computer system employs these one or more processors to execute the processes required to perform the functions desired by the computer's user. Additionally, many computer systems often have to run a large number of different processes. With many processes simultaneously requesting to be executed, the computer system must determine which processes to run based on processor availability and priority of the various processes. The operating system schedules the processes and allocates processor time, often interrupting low priority processes to run processes with a higher priority. In this way the operating system balances the competing needs of various processors to efficiently complete tasks. Some computer systems include only a single processing core, while other computer systems include a plurality of processor cores. Computer systems that include more than one processor core must simultaneous manage scheduling and prioritizing processes across multiple cores.

"The operating system has several mechanisms available to it to ensure the most important tasks are executed in a timely manner. In some systems the operating system will regularly determine, based on priority information or other information, the process that should be executed for the next time interval. This allows high priority processes to be executed before lower priority processes complete, even if the lower priority process began before the higher priority process. Additionally, the operating system may generate asynchronous interrupts in response to various criteria being met. Interrupts may be hardware interrupts, in which the interrupt signal is detected by a physical piece of hardware, like an advance programmable interrupt controller, or software interrupts. The kernel, an important component of the operating system, then interrupts the currently executing processes and allows an interrupt handler to execute. In this way, the computer system can respond quickly to various criteria being met."

In addition to the background information obtained for this patent application, VerticalNews journalists also obtained the inventors' summary information for this patent application: "In accordance with some implementations, a method of measuring processor usage is disclosed. The method is performed on a server system having one or more processors and memory storing one or more programs for execution by the one or more processors. The server system executes, on the one or more processors, one or more processes, wherein each of the one or more first processes is associated with an entity from a group of one or more entities. The server system then receives an interrupt signal at a first predetermined interval. In response to receiving the interrupt signal and for each processor of the one or more processors, the server system interrupts the process currently being executed on the processor. The server system then determines if the interrupted process has an associated counter. In accordance with a determination that the interrupted process has an associated counter, the server system increments the associated counter. The server system then resumes the interrupted process.

"In accordance with some implementations, a method of tracking processor usage of a thread disclosed. The method is performed on a server system having one or more processors and memory storing one or more programs for execution by the one or more processors. The server system creates a thread associated with an entity. The server system then records a pointer to a counter associated with the entity in the thread. The server system then receives, at regular, predetermined intervals, a signal from the operating system being executed on the server system. In response, the server system determines whether the thread is currently being executed by one of the one or more processors. In accordance with a determination that the thread is currently being executed by one processor of the one or more processors the system interrupts the thread being executed and increments a counter associated with the thread.

"In accordance with some implementations, a server system for measuring processor usage is disclosed. The server system has one or more processors and memory storing one or more programs to be executed by the one or more processors. The one or more programs include instructions which cause the system to execute, on the one or more processors, one or more processes, wherein each of the one or more first processes is associated with an entity from a group of one or more entities. The server system then receives an interrupt signal at a first predetermined interval. In response to receiving the interrupt signal and for each processor of the one or more processors, the server system interrupts the process currently being executed on the processor. The server system then determines if the interrupted process has an associated counter. In accordance with a determination that the interrupted process has an associated counter, the server system increments the associated counter. The server system then resumes the interrupted process.

"In accordance with some implementations, a server system for tracking processor usage of a thread disclosed. The server system has one or more processors and memory storing one or more programs to be executed by the one or more processors. The one or more programs include instructions which cause the system to create a thread associated with an entity. The server system then records a pointer to a counter associated with the entity in the thread. The server system then receives, at regular, predetermined intervals, a signal from the operating system being executed on the server system. In response, the server system determines whether the thread is currently being executed by one of the one or more processors. In accordance with a determination that the thread is currently being executed by one processor of the one or more processors the system interrupts the thread being executed and increments a counter associated with the thread.

"In accordance with some implementations, a non-transitory computer readable storage medium storing one or more programs configured for execution by a server system is disclosed. The server system has one or more processors and memory storing one or more programs to be executed by the one or more processors. The one or more programs include instructions which cause the system to execute, on the one or more processors, one or more processes, wherein each of the one or more first processes is associated with an entity from a group of one or more entities. The server system then receives an interrupt signal at a first predetermined interval. In response to receiving the interrupt signal and for each processor of the one or more processors, the server system interrupts the process currently being executed on the processor. The server system then determines if the interrupted process has an associated counter. In accordance with a determination that the interrupted process has an associated counter, the server system increments the associated counter. The server system then resumes the interrupted process.

"In accordance with some implementations, a non-transitory computer readable storage medium storing one or more programs configured for execution by a server system is disclosed. The server system has one or more processors and memory storing one or more programs to be executed by the one or more processors. The one or more programs include instructions which cause the system to create a thread associated with an entity. The server system then records a pointer to a counter associated with the entity in the thread. The server system then receives, at regular, predetermined intervals, a signal from the operating system being executed on the server system. In response, the server system determines whether the thread is currently being executed by one of the one or more processors. In accordance with a determination that the thread is currently being executed by one processor of the one or more processors the system interrupts the thread being executed and increments a counter associated with the thread.

BRIEF DESCRIPTION OF THE DRAWINGS

"The implementations disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. Like reference numerals refer to corresponding parts throughout the drawings.

"FIG. 1 is a block diagram illustrating a distributed storage system, according to some implementations.

"FIG. 2 is a block diagram illustrating components of the distributed storage system, according to some implementations.

"FIG. 3 is a block diagram illustrating the components of a server system, according to some implementations.

"FIG. 4 is a block diagram illustrating the process of tracking processor usage and incrementing processor usage counters according to some implementations.

"FIG. 5 is a flow diagram illustrating the process of gathering statistical data regarding process usage through the use of counters in accordance with some implementations.

"FIG. 6 is a flow diagram illustrating the process of gathering statistical data regarding process usage through the use of counters in accordance with some implementations.

"FIG. 7 is a flow diagram illustrating the process of thread creation and statistical information gathering for the newly created thread in accordance with some implementations."

URL and more information on this patent application, see: Ghemawat, Sanjay; Fikes, Andrew; Taylor, Chris Jorgen. Collecting Processor Usage Statistics. Filed June 4, 2013 and posted January 30, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=469&p=10&f=G&l=50&d=PG01&S1=20140123.PD.&OS=PD/20140123&RS=PD/20140123

Keywords for this news article include: Patents.

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Source: Computer Weekly News


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