By a News Reporter-Staff News Editor at Real Estate Weekly News -- Current study results on Architecture and Code Optimization have been published. According to news reporting out of Gyeonggi Do, South Korea, by VerticalNews editors, research stated, "Coarse-Grained Reconfigurable Architectures (CGRAs) present a potential of high compute throughput with energy efficiency. A CGRA consists of an array of Functional Units (FUs), which communicate with each other through an interconnect network containing transmission nodes and register files."
Our news journalists obtained a quote from the research from the Samsung Advanced Institute of Technology, "To achieve high performance from the software solutions mapped onto CGRAs, modulo scheduling of loops is generally employed. One of the key challenges in modulo scheduling for CGRAs is to explicitly handle routings of operands from a source to a destination operations through various routing resources. Existing modulo schedulers for CGRAs are slow because finding a valid routing is generally a searching problem over a large space, even with the guidance of well-defined cost metrics. Applications in traditional embedded multimedia domains are regarded as relatively tolerant to a slow compile time in exchange for a high-quality solution. However, many rapidly growing domains of applications, such as 3D graphics, require a fast compilation. Entrances of CGRAs to these domains have been blocked mainly due to their long compile time. We attack this problem by utilizing patternized routes, for which resources and time slots for a success can be estimated in advance when a source operation is placed. By conservatively reserving predefined resources at predefined time slots, future routings originating from the source operation are guaranteed."
According to the news editors, the research concluded: "Experiments on a real-world 3D graphics benchmark suite show that our scheduler improves the compile time up to 6,000 times while achieving an average 70% throughputs of the state-of-the-art CGRA modulo scheduler, the Edge-centric Modulo Scheduler (EMS)."
For more information on this research see: Fast Modulo Scheduler Utilizing Patternized Routes for Coarse-Grained Reconfigurable Architectures. ACM Transactions on Architecture and Code Optimization, 2013;10(4):881-1002. ACM Transactions on Architecture and Code Optimization can be contacted at: Assoc Computing Machinery, 2 Penn Plaza, Ste 701, New York, NY 10121-0701, USA.
Our news journalists report that additional information may be obtained by contacting W. Kim, Samsung Adv Inst Technol, Yongin, Gyeonggi Do, South Korea. Additional authors for this research include Y. Choi and H. Park.
Keywords for this news article include: Asia, Gyeonggi Do, South Korea, Architecture and Code Optimization
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