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Researchers Submit Patent Application, "Semiconductor Apparatus and Test Method Thereof", for Approval

March 5, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors KIM, Chul (Icheon-si, KR); LEE, Jong Chern (Icheon-si, KR), filed on December 21, 2012, was made available online on February 20, 2014.

The patent's assignee is Sk Hynix Inc.

News editors obtained the following quote from the background information supplied by the inventors: "The present invention generally relates to a semiconductor apparatus, and more particularly, to a three-dimensional (3D) semiconductor apparatus including a plurality of chips stacked therein.

"In order to increase the integration degree of a semiconductor apparatus, a 3D semiconductor apparatus including a plurality of chips stacked and packaged in a single package has been developed. Recently, a through-silicon via (TSV) method has been used, in which a plurality of stacked chips are electrically connected through TSVs.

"The 3D semiconductor apparatus includes a plurality of TSVs through which the plurality of stacked chips commonly receives various signals. For example, in the case of a memory apparatus, a plurality of stacked chips commonly receive an address signal, signals for various tests, and input/output line and command signals through the TSVs.

"The TSV may have various defects. For example, when the TSV is not completely filled with a conductive material, a void may occur. Furthermore, when a chip is bent or a bump material is moved, a bump contact fail may occur. Furthermore, a crack may occur in the TSV. As described above, the TSV electrically connects a plurality of chips. Therefore, when a defect occurs to open the TSV, the TSV does not perform a normal function. Therefore, a test process of accurately detecting a TSV in which a defect occurred and a repair process of replacing the TSV which has the defect with a normal TSV is required."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "A semiconductor apparatus capable of efficiently testing whether TSVs are normally formed or not is described herein.

"In an embodiment, there is provided a semiconductor apparatus including a plurality of chips stacked therein and first and second TSVs electrically connecting the plurality of chips. The semiconductor apparatus includes: a test voltage application unit configured to apply a test voltage to the first and second TSVs in response to a test mode signal; a first pad configured to output a first test signal outputted from the first TSV; and a second pad configured to output a second test signal outputted from the second TSV.

"In an embodiment, there is provided a semiconductor apparatus which includes a plurality of chips and a plurality of TSVs electrically connecting the plurality of chips and divided into first and second ranks. The semiconductor apparatus: a test voltage application unit configured to apply a test voltage to the plurality of TSVs in response to a test mode signal; a first test signal output unit sequentially connected to the TSVs of the first rank and configured to output a first test signal; a second test signal output unit sequentially connected to the TSVs of the second rank and configured to output a second test signal; a first pad configured to output the first test signal; and a second pad configured to output the second test signal.

"In an embodiment, there is provided a test method of a semiconductor apparatus which includes a plurality of chips and first and second TSVs electrically connecting the plurality of chips. The test method includes the steps of: applying a test voltage to the first and second TSVs; converting signals outputted through the first and second TSVs into first and second digital signals, respectively; and outputting the first and second digital signals to first and second pads, respectively.

"In an embodiment, there is provided a test method of a semiconductor apparatus which includes a plurality of chips and a plurality of TSVs electrically connecting the plurality of chips and divided into first and second ranks. The test method includes the steps of: applying a test voltage to the plurality of TSVs; outputting signals outputted from one of the TSVs of the first rank and one of the TSVs of the second rank to first and second pads, respectively; and outputting signals outputted from another of the TSVs of the first rank and another of the TSVs of the second rank to the first and second pads, respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

"Features, aspects, and embodiments are described in conjunction with the attached drawings, in which:

"FIG. 1 schematically illustrates the configuration of a semiconductor apparatus according to an embodiment;

"FIG. 2 schematically illustrates the configuration of a semiconductor apparatus according to an embodiment; and

"FIG. 3 illustrates the configuration of a first test signal output unit of FIG. 2."

For additional information on this patent application, see: KIM, Chul; LEE, Jong Chern. Semiconductor Apparatus and Test Method Thereof. Filed December 21, 2012 and posted February 20, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=4555&p=92&f=G&l=50&d=PG01&S1=20140213.PD.&OS=PD/20140213&RS=PD/20140213

Keywords for this news article include: Electronics, Sk Hynix Inc, Semiconductor.

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Source: Electronics Newsweekly


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