News Column

Researchers Submit Patent Application, "Method of Preventing Program-Disturbances for a Non-Volatile Semiconductor Memory Device", for Approval

March 5, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Washington, D.C., VerticalNews journalists report that a patent application by the inventors Park, Weon-Ho (Hwaseong-si, KR); Kwon, Hyok-Ki (Hwaseong-si, KR); Kim, Min-Sup (Seoul, KR); Kim, Min-Su (Seongnam-si, KR); Kim, Byoung-Ho (Suwon-si, KR); Kim, Eui-Yeol (Yongin-si, KR); Park, Sang-Hoon (Hwaseong-si, KR); Park, Ji-Hoon (Seongnam-si, KR); Sung, Min-Jee (Suwon-si, KR); Sim, Hyo-Soung (Hwaseong-si, KR); Jeon, Chang-Min (Yongin-si, KR); Jeon, Hee-Seog (Suwon-si, KR), filed on July 11, 2013, was made available online on February 20, 2014.

No assignee for this patent application has been made.

News editors obtained the following quote from the background information supplied by the inventors: "Example embodiments relate generally to a non-volatile semiconductor memory device. More particularly, embodiments of the inventive concepts relate to a method of preventing program-disturbances for a non-volatile semiconductor memory device.

"Semiconductor memory devices may generally be classified into two types: volatile semiconductor memory devices in which data are erased when a power is removed and a non-volatile semiconductor memory device in which data are preserved even in a case where power is removed. Generally, non-volatile semiconductor memory devices have relatively slow read-speed and a relatively slow write-speed as compared to volatile semiconductor memory devices. However, non-volatile semiconductor memory devices enjoy widespread use in situations requiring data retention when power is removed and even in cases when power is in continuing supply.

"An electrically erasable programmable read-only memory (EEPROM) device has become widely used as the non-volatile semiconductor memory device. Typically, the EEPROM device performs a program-operation in a byte unit, and performs an erase-operation in a block unit or in a sector unit. Recently, a 2T-FN (i.e., 2 transistors Fowler-Nordheim) type EEPROM device has been suggested as a flash memory device that performs an erase-operation in a byte unit.

"The 2T-FN type EEPROM device includes a memory cell having 2 transistors, and performs a program-operation and an erase-operation using an F-N (i.e., Fowler-Nordheim) tunneling phenomenon. Here, 2 transistors of the memory cell included in the 2T-FN type EEPROM device are coupled to each other in series. In detail, one transistor of the memory cell included in the 2T-FN type EEPROM device operates as a memory transistor (e.g., floating gate tunnel oxide (FLOTOX) memory transistor). In addition, another transistor of the memory cell included in the 2T-FN type EEPROM device operates as a selection transistor.

"When the 2T-FN type EEPROM device performs a program-operation, a specific voltage bias condition may be applied to a selected memory cell to result in the occurrence of the F-N tunneling phenomenon in the memory transistor. As a result, data may be stored by accumulating electrons in a floating gate. However, in some situations when a program-operation is performed, neighboring non-selected memory cells may be simultaneously programmed (i.e., referred to as program-disturbance). Such program-disturbance can degrade reliability of the 2T-FN type EEPROM device."

As a supplement to the background information on this patent application, VerticalNews correspondents also obtained the inventors' summary information for this patent application: "Some example embodiments provide a method of preventing program-disturbances for a non-volatile semiconductor memory device capable of preventing non-selected memory cells from being programmed when a selected memory cell is programmed in the non-volatile semiconductor memory device, where the non-selected memory cells do not share a selection-line with the selected memory cell.

"According to some example embodiments, a method of preventing program-disturbances for a non-volatile semiconductor memory device having a plurality of memory cells, each memory cell in including a selection transistor and a memory transistor that are coupled in series between a bit-line and a common source-line, where a gate terminal of the selection transistor is coupled to a word-line and a gate terminal of the memory transistor is coupled to a selection-line, is provided. First non-selected memory cells that share a first selection-line with a selected memory cell, and second non-selected memory cells that do not share the first selection-line with the selected memory cell may be determined when the selected memory cell is selected to be programmed among the memory cells. A negative voltage may be applied to second selection-lines that are coupled to the second non-selected memory cells when the selected memory cell is programmed by applying a positive voltage to the first selection-line that is coupled to the selected memory cell.

"In example embodiments, common source-lines that are coupled to the selected memory cell, the first non-selected memory cells, and the second non-selected memory cells may be floated when the selected memory cell is programmed.

"In example embodiments, a negative voltage that is between about -2V and -10V may be applied to a pocket P-well in which the selected memory cell, the first non-selected memory cells, and the second non-selected memory cells are located when the selected memory cell is programmed.

"In example embodiments, a negative voltage of about -6V may be applied to the pocket P-well in which the selected memory cell, the first non-selected memory cells, and the second non-selected memory cells are located when the selected memory cell is programmed.

"In example embodiments, a positive voltage that is between about 6V and about 14V may be applied to a deep N-well that is formed under the pocket P-well when the selected memory cell is programmed.

"In example embodiments, a positive voltage of about 10V may be applied to the deep N-well that is formed under the pocket P-well when the selected memory cell is programmed.

"In example embodiments, a negative voltage that is between about -2V and about -10V may be applied to word-lines that are coupled to the selected memory cell, the first non-selected memory cells, and the second non-selected memory cells when the selected memory cell is programmed.

"In example embodiments, a negative voltage of about -6V may be applied to the word-lines that are coupled to the selected memory cell, the first non-selected memory cells, and the second non-selected memory cells when the selected memory cell is programmed.

"In example embodiments, the negative voltage that is applied to the second selection-lines may be determined to be between about -1V and about -3V when the selected memory cell is programmed.

"In example embodiments, the negative voltage that is applied to the second selection-lines may be determined to be about -2V when the selected memory cell is programmed.

"In example embodiments, the positive voltage that is applied to the first selection-line may be determined to be between about 6V and about 14V when the selected memory cell is programmed.

"In example embodiments, the positive voltage that is applied to the first selection-line may be determined to be about 10V when the selected memory cell is programmed.

"In example embodiments, a negative voltage that is between about -2V and about -10V may be applied to a first bit-line that is coupled to the selected memory cell when the selected memory cell is programmed.

"In example embodiments, a negative voltage of about -6V may be applied to the first bit-line that is coupled to the selected memory cell when the selected memory cell is programmed.

"In example embodiments, the program-disturbances due to an F-N tunneling phenomenon may be prevented in the second non-selected memory cells that share the first bit-line with the selected memory cell when the selected memory cell is programmed.

"In example embodiments, the program-disturbances due to an electron-hole pair phenomenon may be prevented in the second non-selected memory cells that do not share the first bit-line with the selected memory cell when the selected memory cell is programmed.

"In another example embodiment in a method of programming a non-volatile memory device, the device includes a plurality of memory cells, each memory cell including a selection transistor and memory transistor arranged in series between a bit line and a common source line of the memory device, a gate terminal of the selection transistor being coupled to a word line of the device and a gate terminal of the memory transistor being coupled to a selection line of the device. During a programming operation of a selected memory cell by applying a positive voltage to a first selection line that is coupled to the selected memory cell, a negative bias condition is applied to non-selected memory cells by applying a negative voltage to second selection lines that are respectively coupled to the non-selected memory cells.

"In some embodiments, non-selected memory cells are associated with a same bit line as the selected memory cell.

"In some embodiments, the method further comprises applying a negative voltage to the bit line that is associated with the selected memory cell, and applying a GND voltage to bit lines that are unassociated with the selected memory cell.

"In some embodiments, the negative voltage is in a range between about -1V and about -3V.

"In some embodiments, the negative voltage is about -2V.

"Therefore, a method of preventing program-disturbances for a non-volatile semiconductor memory device according to example embodiments may apply a negative bias condition to non-selected memory cells, for example a negative voltage can be applied to selection-lines coupled to the non-selected memory cells, where the non-selected memory cells do not share a selection-line with a selected memory cell, when the selected memory cell is programmed in the non-volatile semiconductor memory device. Thus, the non-selected memory cells may be prevented from becoming inadvertently programmed when the selected memory cell is programmed. As a result, reliability of the non-volatile semiconductor memory device may be greatly improved.

BRIEF DESCRIPTION OF THE DRAWINGS

"Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

"FIG. 1 is a flow diagram illustrating a method of preventing program-disturbances for a non-volatile semiconductor memory device according to example embodiments.

"FIG. 2 is a diagram illustrating an embodiment of a memory cell array to which a method of FIG. 1 is applied.

"FIG. 3 is a cross-sectional diagram illustrating a memory cell included in a memory cell array of FIG. 2.

"FIG. 4 is a diagram illustrating a voltage bias condition for a selected memory cell in the method of FIG. 1.

"FIGS. 5A and 5B are diagrams illustrating a voltage bias condition for a second non-selected memory cell in the method of FIG. 1.

"FIG. 6 is a diagram illustrating a voltage bias condition for a first non-selected memory cell in the method of FIG. 1.

"FIG. 7 is a block diagram illustrating an embodiment of a non-volatile semiconductor memory device employing the method of FIG. 1.

"FIG. 8 is a block diagram illustrating a memory system having a device of FIG. 7.

"FIG. 9 is a diagram illustrating an example in which a host device is coupled to the device of FIG. 7.

"FIG. 10 is a diagram illustrating another example in which a host device is coupled to the device of FIG. 7.

"FIG. 11 is a diagram illustrating still another example in which a host device is coupled to the device of FIG. 7.

"FIG. 12 is a block diagram illustrating an electronic device including the device of FIG. 7."

For additional information on this patent application, see: Park, Weon-Ho; Kwon, Hyok-Ki; Kim, Min-Sup; Kim, Min-Su; Kim, Byoung-Ho; Kim, Eui-Yeol; Park, Sang-Hoon; Park, Ji-Hoon; Sung, Min-Jee; Sim, Hyo-Soung; Jeon, Chang-Min; Jeon, Hee-Seog. Method of Preventing Program-Disturbances for a Non-Volatile Semiconductor Memory Device. Filed July 11, 2013 and posted February 20, 2014. Patent URL: http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.html&r=3716&p=75&f=G&l=50&d=PG01&S1=20140213.PD.&OS=PD/20140213&RS=PD/20140213

Keywords for this news article include: Patents, Electronics, Semiconductor.

Our reports deliver fact-based news of research and discoveries from around the world. Copyright 2014, NewsRx LLC


For more stories covering the world of technology, please see HispanicBusiness' Tech Channel



Source: Electronics Newsweekly


Story Tools