Patent number 8652941 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "The present disclosure relates to a method for dicing substrates, and particularly, to a method of dicing substrate with solder bumps and an underfill layer thereupon.
"Dicing is a process in which a chip-containing substrate is cut into individual dies. The chip-containing substrate typically includes a vertical stack of a semiconductor substrate including semiconductor devices and a metal interconnect structure-containing layer including dielectric material layers and metal interconnect structures embedded therein. Each die typically includes a semiconductor chip, and can be subsequently bonded with another substrate in a bonding process such as flip chip assembly. A diamond blade dicing process has been used in the industry for singulation of dies from the chip-containing substrate.
"A chip-containing substrate includes a semiconductor device layer and a metal interconnect layer that includes metal interconnect structures embedded in a dielectric material layer. Recently, low dielectric constant (low-k) dielectric materials having a dielectric constant less than 3.9 (the dielectric constant of silicon oxide) and porous ultra low-k dielectric materials having a dielectric constant less than 2.8 layers have been employed as the dielectric material embedding the metal interconnect structures. Because such low-k and ultra low-k dielectric materials are prone to structural damage during laser dicing, formation of grooves in the dielectric material layer embedding metal interconnect structures has been recently proposed. Specifically, a laser grooving process can be performed first on the active side of the chip-containing substrate, i.e., the side at which the dielectric material layer embedding metal interconnect structures are located. Low-k and/or ultra low-k dielectric material layers and metallic structures in the dicing channels are ablated by a laser beam. The metallic structures in the dicing channels typically include test structures and alignment structures, and are referred to as kerf structures. Full singulation of the dies is accomplished by cutting through the remaining portion of the chip-containing substrate, i.e., the semiconductor substrate, in the dicing streets with a diamond saw process.
"The two step die singulation process of laser ablation followed by diamond saw dicing requires that the dicing channels are visible for laser grooving. The two step die singulation process can be employed for conventional wafers, i.e., chip-containing substrates, which do not employ a wafer level underfill (WLU) material. As used herein, a 'wafer level underfill,' an 'underfill,' an 'underfill material,' or 'WLU' refers to a underfill material that is applied on a wafer surface or over an array of solder bumps on a wafer, i.e., a chip-containing substrate prior to singulation of the dies therein. However, underfill materials at a thickness comparable with the height of solder bumps (balls), which have a diameter on the order of 10.about.100 microns, are optically opaque. Thus, the two step die singulation process is not compatible with application of an underfill material (such as wafer level underfill (WLU) as known in the art) prior to singulation.
"Specifically, when a wafer level underfill is applied on a wafer, it is very difficult to use the normally used laser grooving method which is critical to prevent damage induced on brittle low K and ultra low K dielectric layers during the wafer sawing process and subsequent solder reflow chip join process for the following reasons.
"Firstly, the laser grooving process needs very precise control in positioning of the laser beam to avoid hitting active features on closely spaced die. The WLU is coated almost the same height as the interconnection solder bumps or slightly thicker than the solder bump height, so even though the transparency of B-stage cured WLU can be good enough to see the solder bumps through a thickness of a few microns, the dicing marks are not visible through the thickness on the order of 10.about.100 microns. Thus, once the WLU is pre-applied on the wafer, the dicing marks on the active surface of wafer, i.e., on the surface of the semiconductor substrate, are not visible.
"Secondly, compared to blade dicing which uses cooling wafer during wafer sawing process, laser grooving does not use any cooling source and the temperature during laser grooving reaches a localized temperature of at least 1,420 degrees Celsius (melting point of Si). Therefore, laser grooving after a WLU coating has been applied to the wafer causes melting and curing of WLU material near the ablation groove edge. The high temperature of laser ablation process results in a very wide heat affected zone, which typically reaches the solder bump areas. Melting and curing of the WLU material necessarily occurs adjacent to the ablation path. The altered physical state of the WLU material affects the flow and curing of WLU during the subsequent flip chip assembly process.
"Therefore, there is a need for a singulation method that is compatible with a substrate having an array of solder bumps and a wafer level underfill (WLU) material thereupon."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "An array of solder bumps is formed on each full semiconductor chip on a chip-containing substrate. In one embodiment, a dielectric material layer embedding metal structures is ablated from the chip-containing substrate by laser grooving, which is performed on dicing channels of the chip-containing substrate. Subsequently, an underfill layer is formed over the dielectric material layer in a pattern that excludes the peripheral areas of the chip-containing substrate. The physically exposed dicing channels at the periphery of the chip-containing substrate can be employed to align a blade to be employed to dice the remaining portions of the chip-containing substrate underneath each dicing channel.
"Laser grooving lines in the dielectric material layer can be formed with precision by employing normal lithography-defined dicing marks for positioning a laser beam. The resulting laser grooves can be relatively shallow, and typically extend from 5 to 15 microns into the semiconductor substrate. The depth of the grooves does not impede spin coating or spray coating of the underfill after the laser grooving process. During subsequent cutting of the chip-containing substrate, a cutting blade can be cooled, for example, by coolants, thereby preventing formation of any heat-affected zone on either side of the blade or damage to adjacent underfill material portions.
"In another embodiment, an underfill layer is formed prior to any laser grooving. A cutting blade is employed to remove the underfill layer from above dicing channels, followed by laser ablation of the dicing channels and subsequent mechanical cutting of the remaining portion of the chip-containing substrate.
"For example, a first groove is formed on an underfill layer by mechanical cutting without generating thermal damage on the underfill layer. A second groove is formed in a dielectric material layer exposed, and/or visible, underneath the first groove by means of a laser radiation without mechanical damage on the dielectric material layer, which can include a porous dielectric material. The semiconductor substrate underneath can be subsequently singulated into dies by mechanical cutting.
"According to an aspect of the present disclosure, a method of manufacturing a semiconductor structure is provided. The method includes: forming a dielectric material layer embedding metal interconnect structures on a surface of a semiconductor substrate; forming a groove in the dielectric material layer along a dicing channel by laser irradiation; forming an underfill layer on the dielectric material layer; and singulating, after forming the underfill layer, the semiconductor substrate into dies by cutting the semiconductor substrate along the dicing channel."
URL and more information on this patent, see: Indyk, Richard F.; Nah, Jae-Woong; Katsurayama,
Keywords for this news article include: Electronics, Semiconductor,
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