The assignee for this patent, patent number 8650748, is
Reporters obtained the following quote from the background information supplied by the inventors: "The present invention relates generally to the packaging of electronic components. More specifically, the invention relates to chip carriers and methods of forming such carriers.
"There are a wide variety of integrated circuit packaging techniques that are commonly used in the semiconductor industry. One common packaging approach contemplates mounting one or more integrated circuits on a structure referred to as a chip carrier having interconnect routing thereon that facilitates electrically connecting the integrated circuit to external devices. One common type of chip carrier is a BGA substrate, which typically takes the form of a dielectric substrate having metal wiring printed on opposing surfaces and conductive vias that extend through the substrate to electrically connect the printed wiring layers. Other common types of chip carrier include silicon interposers, lead frames and flexible carriers.
"Although existing chip carriers work well in a wide variety of applications, a drawback of most chip carriers is that they can be relatively expensive to produce. Therefore, there on ongoing efforts to provide even more cost effective chip carriers that can be used in semiconductor packaging applications."
In addition to obtaining background information on this patent, VerticalNews editors also obtained the inventors' summary information for this patent: "To achieve the foregoing and other objects of the invention, a number of wires (or wires and rods) are arranged in parallel in a wiring fixture. The wires are geometrically positioned in an arrangement that corresponds to the desired contact layout for the desired chip carriers. After the wires are positioned, they are encapsulated to form an encapsulated wiring block. The wiring block is then sliced to form a number of discrete panels. Each panel has one or more device areas that are suitable for use as independent chip carriers. The encapsulant in each panel effectively forms a substrate and the wire segments in each panel form conductive vias that extend through the substrate. The panels/chip carriers are suitable for use in a wide variety of packaging applications.
"In some preferred embodiments, the wire support fixture is arranged to keep the wires in tension during the encapsulation and the wiring fixture is arranged to hold the wires such that the wires extend substantially vertically during the encapsulation. This helps maintain the relative positioning of the wires from panel to panel.
"The chip carrier panels may take a wide variety of forms. In some embodiments, the panels have one or more two dimensional arrays of device areas defined thereon, with each device area being suitable for use as a chip carrier for a separate integrated circuit package after singulation of the panel. The chip carrier panels may be arranged in a form factor that is suitable for use by conventional semiconductor packaging equipment (e.g. in the form factor of conventional semiconductor wafers, lead frame strips, substrate panels, etc.).
"The resulting chip carrier panels are suitable for use in a wide variety of traditional semiconductor packaging applications. For example, a number of dice may be mounted on a first (e.g., top) surface of the panel, such that each die is mounted on an associated device area, with each die being electrically connected to a plurality of the conductive vias in an associated device area. Each device area typically has one or more chip placement areas. An encapsulant material may then be formed over the first surface of the chip carrier panel to encase the dice (e.g. by molding). Thereafter, the panels may be singulated to form a multiplicity of packaged integrated circuit devices, with each singulated device corresponding to an associated device area in the chip carrier panels. When desired, solder bumps (or other I/O structures) may be formed on the conductive vias over the back surface of the panel to provide electrical interconnects suitable for connection to external devices in the singulated devices. In some embodiments, conductive traces that are electrically connected to the conductive vias may be provided on one or both of the surfaces of the carrier to facilitate redistribution of the contacts."
For more information, see this patent: Darbinyan, Artur; Chin, David T.; Sincerbox, Kurt E.. Universal
Keywords for this news article include: Electronics,
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