News Column

Patent Issued for System-On-Chip and Debugging Method

March 5, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventors Lee, Jaegon (Yongin-si, KR); Ahn, Hyunsun (Seoul, KR), filed on May 6, 2011, was published online on February 18, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8656220 is assigned to Samsung Electronics Co., Ltd. (Suwon-Si, Gyeonggi-Do, KR).

The following quote was obtained by the news editors from the background information supplied by the inventors: "The present disclosure relates to electronic circuits, and more particularly, to a system-on-chip (SoC) and a debugging method thereof.

"The number of devices that can be disposed on a single chip is increasing with the advance of semiconductor manufacturing technologies. As the number of devices disposed on a single chip increases, components such as a memory, a processor, and a power controller are integrated into a single chip. A system having various components such as a memory, a processor, and a power controller integrated into a single chip is commonly referred to as a system-on-chip (SoC). Since a system-on-chip (SoC) includes a single chip, it occupies a smaller area than a conventional system. Further, power consumption of the system-on-chip (SoC) is reduced compared to the power consumption of a conventional system."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "According to an exemplary embodiment of the inventive concept, a system-on-chip may include a core, a plurality of power domain blocks, and a power control circuit including a debug circuit. The power control circuit is configured to control a power supplied to the core and each of the power domain blocks, and the debug circuit is configured to debug the power control circuit.

"In an exemplary embodiment of the inventive concept, the debug circuit may further include at least one input/output pin configured to allow the debug circuit to communicate with an entity.

"In an exemplary embodiment of the inventive concept, the system-on-chip may further include an input/output interface configured to communicate with an external entity through a plurality of input/output pins. The debug circuit and the input/output interface may be configured to share at least one of the plurality of input/output pins.

"In an exemplary embodiment of the inventive concept, the system-on chip may further include a debugging pin, different from the at least one input/output pin, configured to allow for debugging of the core.

"In an exemplary embodiment of the inventive concept, the system-on-chip may further include a logic value debugger disposed in the debug circuit, configured to output a voltage level of at least one node of the power control circuit to an external entity, in response to a debug control signal during a debugging operation of the power control circuit.

"In an exemplary embodiment of the inventive concept, the power control circuit may be configured to enter an operation maintenance mode during the debugging operation of the power control circuit.

"In an exemplary embodiment of the inventive concept, the system-on-chip may further include an inserting debugger disposed in the debug circuit, configured to vary a voltage level of at least one node in the power control circuit, in response to a debug control signal during a debugging operation of the power control circuit.

"In an exemplary embodiment of the inventive concept, the system-on-chip may further include a multiplexer disposed in the debug circuit and coupled between an output of a first function block of the power control circuit and an input of a second function block of the power control circuit, and configured to transmit one of the output of the first function block and a debugging input signal from the inserting debugger to the input of the second function block under a control of the inserting debugger.

"In an exemplary embodiment of the inventive concept, the system-on-chip may further include a variation debugger disposed in the debug circuit, configured to output a variation value based on a variation over time of a voltage of at least one node in the power control circuit to an external entity, in response to a debug control signal during a debugging operation of the power control circuit.

"In an exemplary embodiment of the inventive concept, the system-on-chip may further include an inserting debugger disposed in the debug circuit, and a logic value debugger disposed in the debug circuit. The inserting debugger may be configured to vary a voltage level of a first node in the power control circuit. The logic value debugger may be configured to output a voltage level of a second node in the power control circuit, based on the variation of the voltage level of the first node, to an external entity during a debugging operation of the power control circuit.

"In an exemplary embodiment of the inventive concept, the system-on-chip may further include an inserting debugger disposed in the debug circuit, and a variation debugger disposed in the debug circuit. The inserting debugger may be configured to vary a voltage level of a first node in the power control circuit. The variation debugger may be configured to output a time-lapse voltage variation of a second node in the power control circuit, based on the variation of the voltage level of the first node, to an external entity during a debugging operation of the power control circuit.

"In an exemplary embodiment of the inventive concept, the system-on-chip may further include a joint test action group (JTAG) interface, configured to allow the core to be debugged based on a JTAG protocol.

"According to an exemplary embodiment of the inventive concept, a debugging method for a system-on-chip may include debugging an operation of the system-on-chip through a debugging pin disposed on the system-on-chip, and debugging a power control circuit of the system-on-chip through a plurality of input/output pins, different from the debugging pin, disposed on the system-on-chip.

"In an exemplary embodiment of the inventive concept, debugging the power control circuit may include detecting a voltage level of at least one first node in the power control circuit.

"In an exemplary embodiment of the inventive concept, debugging the power control circuit may further include varying the voltage level of at least one node, other than the at least one first node, in the power control circuit.

"In an exemplary embodiment of the inventive concept, debugging the power control circuit may further include monitoring a voltage variation of at least one node, other than the at least one first node, in the power control circuit.

"In an exemplary embodiment of the inventive concept, debugging the power control circuit may further include varying the voltage level of the at least one first node in the power control circuit, and detecting a voltage level of at least one second node in the power control circuit, based on the variation of the voltage level of the at least one first node.

"In an exemplary embodiment of the inventive concept, debugging the power control circuit may further include varying the voltage level of the at least one first node in the power control circuit, and monitoring a voltage variation of at least one second node in the power control circuit, based on the variation of the voltage level of the at least one first node."

URL and more information on this patent, see: Lee, Jaegon; Ahn, Hyunsun. System-On-Chip and Debugging Method. U.S. Patent Number 8656220, filed May 6, 2011, and published online on February 18, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=17&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=805&f=G&l=50&co1=AND&d=PTXT&s1=20140218.PD.&OS=ISD/20140218&RS=ISD/20140218

Keywords for this news article include: Samsung Electronics Co. Ltd.

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Source: Electronics Newsweekly


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