News Column

Patent Issued for Solid-State Imaging Device

March 5, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- A patent by the inventor Ohtsuki, Hirohisa (Toyama, JP), filed on September 12, 2012, was published online on February 18, 2014, according to news reporting originating from Alexandria, Virginia, by VerticalNews correspondents.

Patent number 8653566 is assigned to Panasonic Corporation (Osaka, JP).

The following quote was obtained by the news editors from the background information supplied by the inventors: "A metal oxide semiconductor (MOS) solid-state imaging device used as an imaging device such as a digital still camera includes a sensor in which multiple pixel cells are arranged two-dimensionally (e.g., arranged in an array). If data can be amplified near the sensor when read out from the sensor, it is possible to read out high S/N data. If the high S/N data can be read out, it is possible to obtain the added value that clear image with less noise can be achieved.

"Moreover, as the size of pixel cells has been reduced in recent years following the increase in the number of pixels in an image sensor, the amount of signals which can be generated in the pixel cells has been decreasing. Therefore, improving S/N is strongly demanded. With these backgrounds, various proposals have been made to realize high S/N (e.g., see Patent Literature 1)."

In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventor's summary information for this patent: "Technical Problem

"A solid-state imaging device according to the related art which is recited in Patent Literature 1 is, for example, a MOS solid-state imaging device 1100 as shown in FIG. 7 and includes a pixel array 1101 that converts optical signals to electrical signals, a vertical scanning circuit 1102 that selects the pixel array 1101 in the row direction, and a readout circuit 1103 that reads out signals in the column direction from the pixel array 1101.

"The pixel array 1101 includes pixel cells 1104 that are arranged in an array.

"The pixel cells 1104 each includes a photodiode 1105 that stores electric charges by photoelectric conversion according to an amount of light received, a transfer transistor 1106 that transfers the electric charges stored in the photodiode 1105 to an electric charge storage (FD) according to a transfer control signal TX, an amplifying transistor 1107 that outputs signals in an output line (OUT) 1109 according to a level of the electric charge storage (FD), and a reset transistor 1108 that initializes the electric charge storage (FD) according to a reset signal RES. The drains of the reset transistor 1108 and the amplifying transistor 1107 are connected to a pixel select line (VDD).

"Moreover, FIG. 8 is a layout view of a configuration of the pixel cell 1104.

"The drain of the transfer transistor 1106 and the gate of the amplifying transistor 1107 are connected to an electric charge storage (FD) 1110 and a FD wiring 1111, and the drains of the amplifying transistor 1107 and the reset transistor 1108 are connected to a pixel select line (VDD) 1112.

"A brief description of the operations of the MOS solid-state imaging device 1100 in which the pixel array is provided as above will be given with reference to the timing chart shown in FIG. 9.

"As shown in FIG. 9, the pixel select line (VDD) 1112 is in OFF state at t=t0, which is the initial state. At this time, the electric charge storage (FD) 1110 of the pixel cell is at LOW level and the amplifying transistor 1107 is in OFF state. First, at t=t1, the pixel select line (VDD) 1112 is brought to ON state, i.e., the signal level of the pixel select line (VDD) 1112 is set to be High level. Next, during t=t2 to t3, the reset signal RES of the row to read out is put in ON state, i.e., set to be High level. Thus, the signal level of the electric charge storage (FD) 1110 is reset to be High level. Next, at t=t4, the transfer control signal TX is put in ON state, i.e., set to be High level so that the electric charges stored in the photodiode 1105 by photoelectric conversion is transferred to the electric charge storage (FD) 1110. As shown in t=t4 to t5 in FIG. 9, the electric potential level of the electric charge storage (FD) 1110 changes (decreases). The amplifying transistor 1107 amplifies the changes and the amplified changes are output in the output line (OUT) 1109.

"However, due to the large wiring parasitic capacitance between the electric charge storage (FD) 1110 and the FD wiring 1111 in the solid-state imaging device of the related art, the signal amplitude decreases, thereby leading to a problem that S/N deteriorates. The mechanism will be described below.

"When transferring the electric charges stored in the photodiode 1105 to the FD wiring 1111, a MOS image sensor generates a voltage V according to electric charges Q and the voltage V is transmitted to the amplifying transistor 1107. Here, a transformation is expressed as V=Q/Cfd using a parasitic capacitance Cfd of the FD wiring 1111.

"It is understood from this transformation that the larger the value of parasitic capacitance Cfd of the FD wiring 1111, the smaller the voltage transmitted to the amplifying transistor 1107.

"Here, the parasitic capacitance Cfd of the FD wiring 1111 will be described.

"FIG. 10 is a cross-sectional schematic view taken along the line C-C' of the solid-state imaging device 1100 of the related art, illustrating the positional relationship between the output line (OUT) 1109, the electric charge storage (FD) 1111, and the pixel select line (VDD) 1112. The parasitic capacitance Cfd of the FD wiring 1111 includes the diffusion capacitance of the transfer transistor 1106, the gate capacitance of the amplifying transistor 1107, and parasitic capacitances such as an inter-wiring capacitance.

"With regard to the inter-wiring capacitance, the parasitic capacitance Cfd of the FD wiring 1111 is roughly divided into the capacitance C111 and the fringe capacitance C112, the capacitance C111 occurring between the FD wiring 1111 and the output line (OUT) 1109 provided side by side thereto, and the fringe capacitance C112 occurring between the FD wiring 1111 and the pixel select line (VDD) 1112.

"Here, since the output line (OUT) 1109 performs operations following the operations of the FD wiring 1111, the capacitance C111 which occurs between the FD wiring 1111 and the output line (OUT) 1109 is hardly seen.

"However, the fringe capacitance C112 between the FD wiring 1111 and the pixel select line (VDD) 1112 has a large capacitance value. Although a wiring width is narrow (e.g., 100 nm) to provide more devices for the same substrate especially in the process in recent years, a wiring is greater in height than in width (e.g., 200 nm) to lower wiring resistance and thus the effect is large.

"Thus, as the fringe capacitance C112 increases, the parasitic capacitance Cfd of the FD wiring 1111 also increases. As a result, signal amplitude at the FD wiring 1111 decreases, thereby leading to a problem that S/N deteriorates.

"The present invention has been made to solve the above problems and an object of the present invention is to provide a solid-state imaging device in which high S/N is achieved.

"Solution to Problem

"To solve the above problems, a solid-state imaging device according to an embodiment of the present invention includes a photodiode that is formed in a semiconductor substrate and stores electric charges according to an amount of light received; a transfer transistor that reads out the electric charges from the photodiode; a floating diffusion to which the electric charges read out by the transfer transistor is transferred; a floating diffusion wiring connected to the floating diffusion; an amplifying transistor having a gate connected to the floating diffusion wiring; a power line connected to one of a drain and a source of the amplifying transistor; and a first output signal line connected to the other of the drain and the source of the amplifying transistor, in which the first output signal line includes a first wiring, a second wiring, and a third wiring in a layer having the floating diffusion wiring formed on the semiconductor substrate, the first wiring and the second wiring being formed on the separate sides of the floating diffusion wiring, and the third wiring connecting the first wiring and the second wiring, and the power line is formed above the floating diffusion wiring.

"According to this configuration, the first wiring and the second wiring of a first output signal line are provided side by side with a floating diffusion wiring, and a power line is provided above the floating diffusion wiring. Therefore, the potential difference between the floating diffusion wiring, the first output signal line, and the power line is small, allowing the parasitic capacitance for the floating diffusion wiring to be relatively decreased. Therefore, S/N can be improved.

"Here, the first output signal line may further include a fourth wiring that connects the first wiring and the second wiring, and the floating diffusion wiring may be surrounded by the first wiring, the second wiring, the third wiring, and the fourth wiring.

"According to this configuration, since the first output signal line has the first, second, third, and fourth wirings that surround the four sides of the floating diffusion wiring, it is possible to decrease the parasitic capacitance which occurs between the floating diffusion wiring and another wiring, and improve S/N.

"Here, the first output signal line may be connected to the second output signal line formed between the floating diffusion wiring and the power line.

"According to this configuration, a second output signal line connected to the first output signal line is formed above the floating diffusion wiring and the electric potential of the second output signal line varies with changes in the electric potential of the first output signal line. Therefore, the parasitic capacitance which occurs between the floating diffusion wiring and the first output signal line is smaller than when the first output signal line is not connected to the second output signal line. Therefore, since signal amplitude at the floating diffusion can be increased, the signal amplitude is less likely to be affected by noise, thus allowing S/N to be improved.

"Here, the floating diffusion wiring may be longer in height than in width.

"According to this configuration, the parasitic capacitance between the floating diffusion wiring and the first output signal line is larger than the parasitic capacitance between the floating diffusion wiring and the power line. Therefore, it is possible to suppress the occurrence of the parasitic capacitance between the floating diffusion wiring and a wiring other than the first output signal wiring, and improve S/N.

"Here, a distance between the floating diffusion wiring and the first output signal line may be longer than a distance between the floating diffusion wiring and the power line.

"According to this configuration, since the floating diffusion wiring does not have parasitic capacitance with other output signal lines that do not follow the operations of the floating diffusion wiring, S/N can be improved.

"Advantageous Effects

"According to the present invention, it is possible to provide a solid-state imaging device in which high S/N is achieved."

URL and more information on this patent, see: Ohtsuki, Hirohisa. Solid-State Imaging Device. U.S. Patent Number 8653566, filed September 12, 2012, and published online on February 18, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=69&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3445&f=G&l=50&co1=AND&d=PTXT&s1=20140218.PD.&OS=ISD/20140218&RS=ISD/20140218

Keywords for this news article include: Electronics, Semiconductor, Panasonic Corporation.

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Source: Electronics Newsweekly


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