News Column

Patent Issued for Semiconductor Integrated Circuit

March 5, 2014



By a News Reporter-Staff News Editor at Electronics Newsweekly -- From Alexandria, Virginia, VerticalNews journalists report that a patent by the inventors Komyo, Masayasu (Kanagawa, JP); Iizuka, Yoichi (Kanagawa, JP), filed on June 29, 2011, was published online on February 18, 2014.

The patent's assignee for patent number 8653851 is Renesas Electronics Corporation (Kanagawa, JP).

News editors obtained the following quote from the background information supplied by the inventors: "The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit suitable for power-supply noise reduction.

"In a semiconductor integrated circuit, there has been a problem that data transmission between a data transmitting circuit and a data receiving circuit is not accurately executed when power-supply noise occurs on a plurality of signal lines used for the data transmission between these circuits.

"Therefore, a countermeasure, for example, ODT (On Die Termination) technique has been provided to reduce the power-supply noise on signal lines used for data reception of the data receiving circuit (JEDEC STANDARD, DDR2 SDRAM SPECIFICATION JESD79-2E (Revision of JESD79-2D), April 2008, JEDEC SOLID STATE TECHNOLOGY ASSOCIATION)."

As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "In the related art, the countermeasure such as an ODT function has been provided to reduce the power-supply noise which influences the data receiving circuit. However, the related art provides no countermeasure to reduce the power-supply noise which influences the data transmitting circuit. Normally, the data transmitting circuit includes a data output circuit such as a three-state buffer for transmitting data. The data transmitting circuit controls the data output circuit to output or not to output the data based on a control signal.

"In other words, in the data output circuit, a data transmission mode in which the data output circuit outputs the data and a high impedance mode (HiZ mode) in which the output of the data output circuit is set to a high impedance state (HiZ) are switched based on the control signal. The data transmitting circuit controls the data output circuit to be in the data transmission mode when transmitting the data and to be in the HiZ mode when not transmitting the data.

"The data output circuit outputs last data output by the data output circuit in a last data transmission mode during the period between the time when the mode is switched from the HiZ mode to the data transmission mode and the time when the data output circuit starts to output next data. In this case, the data output circuits provided to the signal lines may output the biased data whose voltage level is H or L level.

"More particularly, in the case where the IO areas (for example, IO buffers) corresponding to the signal lines are arranged adjacent to each other, the power-supply noise occurring on each signal line is amplified when the data output circuits start to output the data having the same potential at the same time from the HiZ mode. Therefore, the present inventors have found a problem in the related art that, as described above, it is impossible for the data transmitting circuit to transmit the data accurately.

"An exemplary aspect of the present invention is a semiconductor integrated circuit including:

"a data transmitting circuit that transmits transmission data in parallel through a plurality of signal lines; and

"a data receiving circuit that receives the transmission data, in which the data transmitting circuit includes: a plurality of data output circuits that output the transmission data in a data transmission mode or set an output to a high impedance state in a high impedance mode, the data output circuits being provided to the corresponding signal lines; a plurality of data selection circuits that select one of the transmission data and fixed data preliminarily set and outputs the selected data to the corresponding data output circuits; and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the high impedance mode to the data transmission mode and a time when the data output circuits start to output the transmission data.

"With the circuit structure as described above, it is possible to transmit data accurately by reducing the amplification of the power-supply noise.

"According to an exemplary aspect of the present invention, it is possible to provide a semiconductor integrated circuit capable of transmitting data accurately."

For additional information on this patent, see: Komyo, Masayasu; Iizuka, Yoichi. Semiconductor Integrated Circuit. U.S. Patent Number 8653851, filed June 29, 2011, and published online on February 18, 2014. Patent URL: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=64&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3161&f=G&l=50&co1=AND&d=PTXT&s1=20140218.PD.&OS=ISD/20140218&RS=ISD/20140218

Keywords for this news article include: Semiconductor, Data Transmission, Renesas Electronics Corporation.

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Source: Electronics Newsweekly


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