Patent number 8653603 is assigned to
The following quote was obtained by the news editors from the background information supplied by the inventors: "The present disclosure herein relates to semiconductor devices and methods of fabricating the same, and more particularly, to a semiconductor devices with cell and peripheral regions and methods of fabricating the same.
"With increased integration, HEIP (Hot Electron Induced Punch-through) characteristics for p-MOS transistors of DRAM (Dynamic Random Access Memory) devices may deteriorate. A structure expanding a gate electrode adjacent to a field region has been proposed to address this problem. However, such a structure may cause a deterioration in reliability, operation speed and the like."
In addition to the background information obtained for this patent, VerticalNews journalists also obtained the inventors' summary information for this patent: "In some embodiments, a semiconductor device includes a substrate including a memory cell region and a peripheral region and a field pattern including an insulating region disposed on a nitride liner in a trench in the substrate adjacent an active region. The field pattern and the active region extend in parallel through the cell and peripheral regions. The device also includes a transistor in the peripheral region including a source/drain region in the active region. The device further includes an insertion pattern including an elongate conductive region disposed in the substrate and extending along a boundary between the field pattern and the active region in the peripheral region.
"The insertion pattern may include a lower conductive portion and an upper insulating portion. The nitride liner may not extend between sidewalls of the insertion pattern and the field pattern. In some embodiments, the device further includes a first contact electrically connected to the source/drain regions of the transistor and a second contact electrically connected to the conductive region of the insertion pattern.
"In some embodiments, the field pattern includes first and second field patterns including respective insulating regions disposed on nitride liners in respective trenches in the substrate and extending in parallel through the cell and peripheral regions. The active region is disposed between the first and second field patterns. The insertion pattern includes first and second insertion patterns, each including an elongate conductive region disposed in the substrate and extending along respective first and second boundaries between active region and second first and second field patterns. The transistor may include a square-ring shaped gate electrode including opposing first line patterns extending in parallel with the active pattern and overlying the first and second insertion patterns and second opposing line patterns extending across the active pattern.
"Further embodiments provide a method of fabricating a semiconductor device. A field pattern is formed including an insulating region disposed on a nitride liner in a trench in a substrate adjacent an active region, the field pattern and the active region extending in parallel through cell and peripheral regions of the substrate. A transistor is formed in the peripheral region including a source/drain region in the active region. An insertion pattern is formed including an elongate conductive region disposed in the substrate and extending along a boundary between the field pattern and the active region in the peripheral region.
"Further embodiments provide a method in which a plurality of first trenches are formed extending in parallel along a first direction through a cell region and a peripheral region of a substrate to define a plurality of active regions extending in parallel between the trenches. Nitride liners are formed in respective ones of the first trenches. Insulating regions are formed on respective ones of the nitride liners in the first trenches to form a plurality of field patterns extending in parallel along the first direction through the cell region and the peripheral region. Portions of the substrate, the nitride liner and the insulating regions are removed to form second trenches extending along the first direction at boundaries of the active regions in the peripheral region and third trenches extending along a second direction transverse to the first direction in the cell region through the active regions. Conductive regions are formed in bottom portions of the second and third trenches. Source/drain regions are formed in the active regions on first and second sides of the conductive regions in the third trenches. A gate electrode may be formed in the peripheral region extending along the second direction and crossing the conductive regions in the second trenches."
URL and more information on this patent, see: Park, Won-Kyung;
Keywords for this news article include: Semiconductor,
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