The patent's assignee for patent number 8656336 is
News editors obtained the following quote from the background information supplied by the inventors: "The disclosed subject matter relates generally to integrated circuit device manufacturing and, more particularly, to a pattern based method for identifying design for manufacturing improvement in a semiconductor device.
"The formation of various integrated circuit (IC) structures on a wafer often relies on lithographic processes, sometimes referred to as photolithography, or simply lithography. As is well known, lithographic processes can be used to transfer a pattern of a photomask (i.e., also referred to as a mask or a reticle) to a wafer. There is a pervasive trend in the art of IC fabrication to increase the density with which various structures are arranged. For example, feature size, line width, and the separation between features and lines are becoming increasingly smaller. In these sub-micron processes, yield is affected by factors such as mask pattern fidelity, optical proximity effects, and photoresist processing. Some of the more prevalent concerns include line end pullback, corner rounding and line-width variations. These concerns are largely dependent on local pattern density and topology.
"Integrated circuit devices are formed in layers. Interconnect structures, such as trenches, vias, etc. are used to form interlayer connections between features, such as lines. For example, a via may be used to connect a line feature, such as a gate electrode, in a first layer to a metal line feature in another layer formed above the first layer. The accuracy at which the interconnect structures align with underlying features affects the functionality of the device. Misalignments may cause performance degradation and or device failure. Misalignment errors may arise from misregistration during the patterning processes to form the features of the various layers (i.e., the layers are not aligned accurately) or due to variations in the dimensions of the features themselves (e.g., due to proximity effects).
"Integrated circuit devices are typically designed with some degree of margin to allow for some degree of misalignment. In general, increasing the margin increases the manufacturability of the device by reducing the likelihood of a yield issue. However, there is a trade-off between margin and pattern density. Increased dimensions result in decreased pattern densities. There are design rules for an integrated circuit that specify parameters such as how closely adjacent features may be formed. Design rules are specified in manner that takes into account manufacturing limitations such as overlay and/or optical proximity effects. Increasing the margin for a given feature may result in the violation of one or more of the design rules unless the spacing is increased.
"During the design process various tools may be used to check the design. A design rule checker may be used to verify that none of the patterns violates a design rule. A design for manufacturability (DFM) tool may be used to generate a score for the design representing the likelihood that the device can be manufactured without pattern based yield issues. The DFM unit may identify regions or patterns in the device that have a relatively significant likelihood of being improperly formed during the fabrication process, commonly referred to as 'hot spots.' Once, a hot spot has been identified, a designer manually evaluates the region and may attempt to change one or more of the dimensions of the features in the region to improve manufacturability. After these changes, the analysis of the design must be repeated to identify if any improvements in the DFM score have been achieved. This design revision process is time consuming and iterative, as it is difficult to estimate the DFM improvements that will from the design changes.
"This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "The following presents a simplified summary of the disclosed subject matter in order to provide a basic understanding of some aspects of the disclosed subject matter. This summary is not an exhaustive overview of the disclosed subject matter. It is not intended to identify key or critical elements of the disclosed subject matter or to delineate the scope of the disclosed subject matter. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
"One aspect of the disclosed subject matter is seen in a method including receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. Outer markers are generated in the computing apparatus for at least a subset of the features based on the proximity of the features to one another and spacing requirements. Features are identified in the computing apparatus where the associated outer marker has at least one dimension greater than the dimensions specified for the feature.
"Another aspect of the disclosed subject matter is seen a method that includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of at least a first feature. An outer marker for the first feature is generated in the computing apparatus having at least one dimension greater than the dimensions specified for the first feature. A first weighting factor for the first feature is generated in the computing apparatus based on the outer marker."
For additional information on this patent, see: Pathak, Piyush; Malik, Shobhit; Madhavan, Sriram. Pattern Based Method for Identifying Design for Manufacturing Improvement in a Semiconductor Device. U.S. Patent Number 8656336, filed
Keywords for this news article include: Electronics, Semiconductor,
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