The patent's assignee for patent number 8652963 is
News editors obtained the following quote from the background information supplied by the inventors: "The transistor is the basic building block of all present day integrated circuit (IC) designs and devices. Fundamentally, a transistor is an electronic switch which includes a source region, a drain region electrically insulated from the source, and a control gate. A control voltage applied to the gate electrode selectively controls electrical communication between the source and drain electrodes, thereby controlling the binary ('on' and 'off') state of the device.
"A common integrated circuit implementation involves interconnecting a large number of field effect transistors (FETs), typically metal oxide semiconductor field effect transistors (MOSFETs), resulting in a highly complex, three dimensional integrated circuit device. The mechanical and electrical integrity of the source, drain, and gate electrodes of these transistors can significantly impact device performance, device variation, and manufacturing yield.
"As the number and complexity of functions implemented in IC devices (such as microprocessors and memory devices) increases, more and more transistors must be incorporated into the underlying integrated circuit chip. The fabrication of large scale integrated circuit devices presents a number of competing manufacturing and processing challenges.
"Presently known methods of fabricating electrical contacts for drain, source, and gate electrodes involve the use of a 'Silicide' layer (also called a 'metal Silicide' layer). More particularly, a thin layer of metal (such as Nickel, Erbium, Cobalt, Titanium, Platinum, Ytterbium, and their alloys) is deposited onto the substrate surface, for example by physical vapor deposition (PVD), chemical vapor deposition (CVD), or plasma enhanced chemical vapor deposition (PECVD). A thermal annealing process, such as rapid thermal annealing (RTA), facilitates reaction of the metal and substrate, resulting in formation of a metal Silicide layer (e.g. nickel Silicide).
"It is desired to produce a metal Silicide layer having a uniform thickness across the surface of the wafer, and particularly in contact trenches of different dimensions (i.e., on the bottom surfaces of both wide and narrow canyons). However, current methods in manufacturing by physical vapor deposition (PVD) do not reliably form a uniformly thin metal Silicide layer, especially in the presence of high aspect ratio structures. Rather, conventional methods tend to produce metal silicide layers with a greater thickness at the bottom of wide trenches, and a correspondingly lesser thickness at the bottom of narrower trenches. This can lead to device variation and may ultimately adversely affect manufacturing yield.
"Accordingly, a need exists to provide methods for fabricating MOSFET ICs having a metal silicide layer which is of uniform thickness across the device surface, and particularly in contact trenches having different dimensions.
"Furthermore, other desirable features and characteristics of various embodiments will become apparent from the subsequent summary, detailed description, and the appended claims, taken in conjunction with the accompanying drawings, brief description of the drawings, the foregoing technical field and this background of the invention."
As a supplement to the background information on this patent, VerticalNews correspondents also obtained the inventors' summary information for this patent: "In accordance with one embodiment, a method for fabricating a MOSFET IC having a metal silicide layer of substantially uniform thickness at the bottoms of both wide and narrow contact trenches includes depositing a layer of metal over the substrate and forming an amorphous alloy layer of silicon intermixed with metal at the silicon/metal interface in the range of about 1-5 nanometers. The unreacted metal is then removed from the substrate surface, and the substrate is exposed a thermal process to convert the amorphous alloy layer into silicide with a thickness of about 2-10 nanometers. The thermal treatment can be done by furnace annealing, rapid thermal annealing (RTA), or Laser annealing (LSA). The RTA condition can be in the range of about 200-500 C for about 30 seconds.
"In accordance with one embodiment the unreacted metal is removed from the substrate surface using a wet etch process which selectively etches the deposited metal layer but does not substantially etch the amorphous alloy layer."
For additional information on this patent, see: Yang, Bin; Lavoie, Christian; Alptekin, Emre; Ozcan, Ahmet S.; Tran, Cung D.; Raymond, Mark. MOSFET Integrated Circuit with Uniformly Thin Silicide Layer and Methods for Its Manufacture. U.S. Patent Number 8652963, filed
Keywords for this news article include: Nanotechnology,
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